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Use correct flag for GPIOC IDR check.

This commit is contained in:
Dominic Clifton 2015-01-31 22:27:45 +01:00
parent 01b2ce0b36
commit 2a37e26715
1 changed files with 1 additions and 1 deletions
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2
lib/main/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
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@ -145,7 +145,7 @@ void SetSysClock(bool overclock)
// On CJMCU new revision boards (Late 2014) bit 15 of GPIOC->IDR is '1'.
RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
#else
RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
RCC_CFGR_PLLMUL = GPIOC->IDR & GPIO_IDR_IDR15 ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
#endif
switch (clocksrc) {
case SRC_HSE: