From 382356a09c616a2eb563de90eff39fb2473c3319 Mon Sep 17 00:00:00 2001 From: Dominic Clifton Date: Mon, 2 Jun 2014 11:10:19 +0100 Subject: [PATCH] STM32F30x - Fix USB VCP initialisation. --- .../CM1/DeviceSupport/ST/STM32F30x/system_stm32f30x.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/main/CMSIS/CM1/DeviceSupport/ST/STM32F30x/system_stm32f30x.c b/lib/main/CMSIS/CM1/DeviceSupport/ST/STM32F30x/system_stm32f30x.c index 8dd068b8f..e1b4b2e3c 100644 --- a/lib/main/CMSIS/CM1/DeviceSupport/ST/STM32F30x/system_stm32f30x.c +++ b/lib/main/CMSIS/CM1/DeviceSupport/ST/STM32F30x/system_stm32f30x.c @@ -51,17 +51,17 @@ *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 + * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * APB1 Prescaler | 2 *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 8000000 + * HSE Frequency(Hz) | 12000000 *---------------------------------------------------------------------------- - * PLLMUL | 9 + * PLLMUL | 6 *----------------------------------------------------------------------------- * PREDIV | 1 *----------------------------------------------------------------------------- - * USB Clock | DISABLE + * USB Clock | ENABLE *----------------------------------------------------------------------------- * Flash Latency(WS) | 2 *----------------------------------------------------------------------------- @@ -331,7 +331,7 @@ void SetSysClock(void) /* PLL configuration */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); /* Enable PLL */ RCC->CR |= RCC_CR_PLLON;