From 3b1f423c494886f4a01b9344a7b8a27588e72e57 Mon Sep 17 00:00:00 2001 From: "Larry (TBS)" Date: Tue, 9 Jun 2015 19:06:52 +0800 Subject: [PATCH] COLIBRI RACE support --- Makefile | 19 +- src/main/config/config.c | 2 +- src/main/drivers/accgyro_spi_mpu6500.c | 2 +- src/main/drivers/accgyro_spi_mpu6500.h | 0 src/main/drivers/bus_spi.c | 2 + src/main/drivers/light_led_stm32f30x.c | 10 + src/main/drivers/pwm_mapping.c | 48 +++ src/main/drivers/pwm_rx.c | 1 - src/main/drivers/timer.c | 26 ++ src/main/io/gps.c | 2 +- src/main/sensors/initialisation.c | 5 + src/main/target/CJMCU/hardware_revision.c | 4 + src/main/target/CJMCU/hardware_revision.h | 2 + .../target/COLIBRI_RACE/hardware_revision.c | 60 +++ .../target/COLIBRI_RACE/hardware_revision.h | 21 + .../target/COLIBRI_RACE/system_stm32f30x.c | 372 ++++++++++++++++++ .../target/COLIBRI_RACE/system_stm32f30x.h | 76 ++++ src/main/target/COLIBRI_RACE/target.h | 168 ++++++++ src/main/target/NAZE/hardware_revision.c | 4 + src/main/target/NAZE/hardware_revision.h | 2 + 20 files changed, 819 insertions(+), 7 deletions(-) mode change 100644 => 100755 Makefile mode change 100644 => 100755 src/main/config/config.c mode change 100644 => 100755 src/main/drivers/accgyro_spi_mpu6500.c mode change 100644 => 100755 src/main/drivers/accgyro_spi_mpu6500.h mode change 100644 => 100755 src/main/drivers/pwm_mapping.c mode change 100644 => 100755 src/main/drivers/timer.c mode change 100644 => 100755 src/main/io/gps.c mode change 100644 => 100755 src/main/sensors/initialisation.c mode change 100644 => 100755 src/main/target/CJMCU/hardware_revision.c mode change 100644 => 100755 src/main/target/CJMCU/hardware_revision.h create mode 100755 src/main/target/COLIBRI_RACE/hardware_revision.c create mode 100755 src/main/target/COLIBRI_RACE/hardware_revision.h create mode 100755 src/main/target/COLIBRI_RACE/system_stm32f30x.c create mode 100755 src/main/target/COLIBRI_RACE/system_stm32f30x.h create mode 100755 src/main/target/COLIBRI_RACE/target.h mode change 100644 => 100755 src/main/target/NAZE/hardware_revision.c mode change 100644 => 100755 src/main/target/NAZE/hardware_revision.h diff --git a/Makefile b/Makefile old mode 100644 new mode 100755 index a7cd3433f..d320d8888 --- a/Makefile +++ b/Makefile @@ -38,7 +38,7 @@ FLASH_SIZE ?= FORKNAME = cleanflight -VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 CC3D CJMCU EUSTM32F103RC SPRACINGF3 PORT103R SPARKY ALIENWIIF1 ALIENWIIF3 +VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 CC3D CJMCU EUSTM32F103RC SPRACINGF3 PORT103R SPARKY ALIENWIIF1 ALIENWIIF3 COLIBRI_RACE # Valid targets for OP BootLoader support OPBL_VALID_TARGETS = CC3D @@ -49,7 +49,7 @@ ifeq ($(TARGET),$(filter $(TARGET),CJMCU)) FLASH_SIZE = 64 else ifeq ($(TARGET),$(filter $(TARGET),NAZE CC3D ALIENWIIF1 OLIMEXINO)) FLASH_SIZE = 128 -else ifeq ($(TARGET),$(filter $(TARGET),EUSTM32F103RC PORT103R STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 SPARKY ALIENWIIF3)) +else ifeq ($(TARGET),$(filter $(TARGET),EUSTM32F103RC PORT103R STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 SPARKY ALIENWIIF3 COLIBRI_RACE)) FLASH_SIZE = 256 else $(error FLASH_SIZE not configured for target) @@ -72,7 +72,7 @@ VPATH := $(SRC_DIR):$(SRC_DIR)/startup USBFS_DIR = $(ROOT)/lib/main/STM32_USB-FS-Device_Driver USBPERIPH_SRC = $(notdir $(wildcard $(USBFS_DIR)/src/*.c)) -ifeq ($(TARGET),$(filter $(TARGET),STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 SPARKY ALIENWIIF3)) +ifeq ($(TARGET),$(filter $(TARGET),STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 SPARKY ALIENWIIF3 COLIBRI_RACE)) STDPERIPH_DIR = $(ROOT)/lib/main/STM32F30x_StdPeriph_Driver @@ -510,6 +510,19 @@ CHEBUZZF3_SRC = \ $(HIGHEND_SRC) \ $(COMMON_SRC) +COLIBRI_RACE_SRC = \ + $(STM32F30x_COMMON_SRC) \ + drivers/display_ug2864hsweg01.c \ + drivers/accgyro_spi_mpu6500.c \ + drivers/barometer_ms5611.c \ + drivers/compass_ak8975.c \ + drivers/compass_hmc5883l.c \ + drivers/serial_usb_vcp.c \ + hardware_revision.c \ + $(HIGHEND_SRC) \ + $(COMMON_SRC) \ + $(VCP_SRC) + SPARKY_SRC = \ $(STM32F30x_COMMON_SRC) \ drivers/display_ug2864hsweg01.c \ diff --git a/src/main/config/config.c b/src/main/config/config.c old mode 100644 new mode 100755 index 91f1ad949..6764ad4ab --- a/src/main/config/config.c +++ b/src/main/config/config.c @@ -361,7 +361,7 @@ static void resetConf(void) masterConfig.version = EEPROM_CONF_VERSION; masterConfig.mixerMode = MIXER_QUADX; featureClearAll(); -#if defined(CJMCU) || defined(SPARKY) +#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) featureSet(FEATURE_RX_PPM); #endif diff --git a/src/main/drivers/accgyro_spi_mpu6500.c b/src/main/drivers/accgyro_spi_mpu6500.c old mode 100644 new mode 100755 index f293d7104..08bd194ac --- a/src/main/drivers/accgyro_spi_mpu6500.c +++ b/src/main/drivers/accgyro_spi_mpu6500.c @@ -99,6 +99,7 @@ static bool mpu6500Detect(void) uint8_t tmp; mpu6500ReadRegister(MPU6500_RA_WHOAMI, &tmp, 1); + if (tmp != MPU6500_WHO_AM_I_CONST) return false; @@ -165,7 +166,6 @@ static void mpu6500AccRead(int16_t *accData) static void mpu6500GyroInit(void) { - #ifdef NAZE gpio_config_t gpio; // MPU_INT output on rev5 hardware (PC13). rev4 was on PB13, conflicts with SPI devices diff --git a/src/main/drivers/accgyro_spi_mpu6500.h b/src/main/drivers/accgyro_spi_mpu6500.h old mode 100644 new mode 100755 diff --git a/src/main/drivers/bus_spi.c b/src/main/drivers/bus_spi.c index f2b0cb244..7eda0a6a0 100644 --- a/src/main/drivers/bus_spi.c +++ b/src/main/drivers/bus_spi.c @@ -34,6 +34,7 @@ static volatile uint16_t spi3ErrorCount = 0; #ifdef USE_SPI_DEVICE_1 +#ifndef SPI1_GPIO #define SPI1_GPIO GPIOA #define SPI1_GPIO_PERIPHERAL RCC_AHBPeriph_GPIOB #define SPI1_SCK_PIN GPIO_Pin_5 @@ -45,6 +46,7 @@ static volatile uint16_t spi3ErrorCount = 0; #define SPI1_MOSI_PIN GPIO_Pin_7 #define SPI1_MOSI_PIN_SOURCE GPIO_PinSource7 #define SPI1_MOSI_CLK RCC_AHBPeriph_GPIOA +#endif void initSpi1(void) { diff --git a/src/main/drivers/light_led_stm32f30x.c b/src/main/drivers/light_led_stm32f30x.c index 0e6d47a1d..cce6a0650 100644 --- a/src/main/drivers/light_led_stm32f30x.c +++ b/src/main/drivers/light_led_stm32f30x.c @@ -45,6 +45,12 @@ void ledInit(void) { .gpio = LED1_GPIO, .cfg = { LED1_PIN, Mode_Out_PP, Speed_2MHz } + }, +#endif +#ifdef LED2 + { + .gpio = LED2_GPIO, + .cfg = { LED2_PIN, Mode_Out_PP, Speed_2MHz } } #endif }; @@ -57,9 +63,13 @@ void ledInit(void) #ifdef LED1 RCC_AHBPeriphClockCmd(LED1_PERIPHERAL, ENABLE); #endif +#ifdef LED2 + RCC_AHBPeriphClockCmd(LED2_PERIPHERAL, ENABLE); +#endif LED0_OFF; LED1_OFF; + LED2_OFF; for (i = 0; i < gpio_count; i++) { gpioInit(gpio_setup[i].gpio, &gpio_setup[i].cfg); diff --git a/src/main/drivers/pwm_mapping.c b/src/main/drivers/pwm_mapping.c old mode 100644 new mode 100755 index aa6c6109a..9ef45a964 --- a/src/main/drivers/pwm_mapping.c +++ b/src/main/drivers/pwm_mapping.c @@ -241,6 +241,48 @@ static const uint16_t airPWM[] = { }; #endif +#ifdef COLIBRI_RACE +static const uint16_t multiPPM[] = { + PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM6 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM7 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM8 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM9 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM10 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM11 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + 0xFFFF +}; + +static const uint16_t multiPWM[] = { + // TODO + 0xFFFF +}; + +static const uint16_t airPPM[] = { + PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input + PWM2 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM3 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM4 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM5 | (MAP_TO_MOTOR_OUTPUT << 8), + PWM6 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM7 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM8 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM9 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM10 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + PWM11 | (MAP_TO_MOTOR_OUTPUT << 8), // Swap to servo if needed + 0xFFFF +}; + +static const uint16_t airPWM[] = { + // TODO + 0xFFFF +}; +#endif + #if defined(SPARKY) || defined(ALIENWIIF3) static const uint16_t multiPPM[] = { PWM11 | (MAP_TO_PPM_INPUT << 8), // PPM input @@ -478,6 +520,12 @@ pwmOutputConfiguration_t *pwmInit(drv_pwm_config_t *init) type = MAP_TO_SERVO_OUTPUT; #endif +#if defined(COLIBRI_RACE) + // remap PWM1+2 as servos + if ((timerIndex == PWM6 || timerIndex == PWM7 || timerIndex == PWM8 || timerIndex == PWM9) && timerHardwarePtr->tim == TIM2) + type = MAP_TO_SERVO_OUTPUT; +#endif + #if defined(SPARKY) // remap PWM1+2 as servos if ((timerIndex == PWM1 || timerIndex == PWM2) && timerHardwarePtr->tim == TIM15) diff --git a/src/main/drivers/pwm_rx.c b/src/main/drivers/pwm_rx.c index ba59bd865..90dd28a0b 100644 --- a/src/main/drivers/pwm_rx.c +++ b/src/main/drivers/pwm_rx.c @@ -359,4 +359,3 @@ uint16_t pwmRead(uint8_t channel) { return captures[channel]; } - diff --git a/src/main/drivers/timer.c b/src/main/drivers/timer.c old mode 100644 new mode 100755 index a2c84663f..bf9d839e6 --- a/src/main/drivers/timer.c +++ b/src/main/drivers/timer.c @@ -115,6 +115,32 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { #endif +#ifdef COLIBRI_RACE +const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { + { TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 0, Mode_AF_PP_PD, GPIO_PinSource8, GPIO_AF_6}, // PWM1 - PA8 + + { TIM3, GPIOC, Pin_6, TIM_Channel_1, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource6, GPIO_AF_2}, // PWM2 - PC6 + { TIM3, GPIOC, Pin_7, TIM_Channel_2, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource7, GPIO_AF_2}, // PWM3 - PC7 + { TIM3, GPIOC, Pin_8, TIM_Channel_3, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource8, GPIO_AF_2}, // PMW4 - PC8 + { TIM3, GPIOC, Pin_9, TIM_Channel_4, TIM3_IRQn, 1, Mode_AF_PP, GPIO_PinSource9, GPIO_AF_2}, // PWM5 - PC9 + + { TIM2, GPIOA, Pin_0, TIM_Channel_1, TIM2_IRQn, 1, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_1}, // PWM6 - PA0 + { TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 1, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_1}, // PWM7 - PA1 + { TIM2, GPIOA, Pin_2, TIM_Channel_3, TIM2_IRQn, 1, Mode_AF_PP, GPIO_PinSource2, GPIO_AF_1}, // PWM8 - PA2 + { TIM2, GPIOA, Pin_3, TIM_Channel_4, TIM2_IRQn, 1, Mode_AF_PP, GPIO_PinSource3, GPIO_AF_1}, // PWM9 - PA3 + + { TIM15, GPIOB, Pin_14, TIM_Channel_1, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP_PD, GPIO_PinSource14, GPIO_AF_1}, // PWM10 - PB14 + { TIM15, GPIOB, Pin_15, TIM_Channel_2, TIM1_BRK_TIM15_IRQn, 1, Mode_AF_PP_PD, GPIO_PinSource15, GPIO_AF_1}, // PWM11 - PB15 +}; + +#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(15)) + +#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3) +#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15) +#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOC) + +#endif + #ifdef CHEBUZZF3 const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { // INPUTS CH1-8 diff --git a/src/main/io/gps.c b/src/main/io/gps.c old mode 100644 new mode 100755 index da701f751..c5ebe3b99 --- a/src/main/io/gps.c +++ b/src/main/io/gps.c @@ -238,7 +238,7 @@ void gpsInit(serialConfig_t *initialSerialConfig, gpsConfig_t *initialGpsConfig) portMode_t mode = MODE_RXTX; // only RX is needed for NMEA-style GPS if (gpsConfig->provider == GPS_NMEA) - mode &= ~MODE_TX; + mode &= ~MODE_TX; // no callback - buffer will be consumed in gpsThread() gpsPort = openSerialPort(gpsPortConfig->identifier, FUNCTION_GPS, NULL, gpsInitData[gpsData.baudrateIndex].baudrateIndex, mode, SERIAL_NOT_INVERTED); diff --git a/src/main/sensors/initialisation.c b/src/main/sensors/initialisation.c old mode 100644 new mode 100755 index 8400b1f1a..e028bc0dd --- a/src/main/sensors/initialisation.c +++ b/src/main/sensors/initialisation.c @@ -36,6 +36,7 @@ #include "drivers/accgyro_l3gd20.h" #include "drivers/accgyro_lsm303dlhc.h" +#include "drivers/bus_spi.h" #include "drivers/accgyro_spi_mpu6000.h" #include "drivers/accgyro_spi_mpu6500.h" @@ -74,6 +75,7 @@ extern acc_t acc; uint8_t detectedSensors[MAX_SENSORS_TO_DETECT] = { GYRO_NONE, ACC_NONE, BARO_NONE, MAG_NONE }; + const mpu6050Config_t *selectMPU6050Config(void) { #ifdef NAZE @@ -225,6 +227,9 @@ bool detectGyro(uint16_t gyroLpf) case GYRO_SPI_MPU6500: #ifdef USE_GYRO_SPI_MPU6500 +#ifdef USE_HARDWARE_REVISION_DETECTION + spiBusInit(); +#endif #ifdef NAZE if (hardwareRevision == NAZE32_SP && mpu6500SpiGyroDetect(&gyro, gyroLpf)) { #ifdef GYRO_SPI_MPU6500_ALIGN diff --git a/src/main/target/CJMCU/hardware_revision.c b/src/main/target/CJMCU/hardware_revision.c old mode 100644 new mode 100755 index f424ee2af..88cbbae1e --- a/src/main/target/CJMCU/hardware_revision.c +++ b/src/main/target/CJMCU/hardware_revision.c @@ -51,3 +51,7 @@ void detectHardwareRevision(void) void updateHardwareRevision(void) { } + +void spiBusInit(void) +{ +} diff --git a/src/main/target/CJMCU/hardware_revision.h b/src/main/target/CJMCU/hardware_revision.h old mode 100644 new mode 100755 index 0b5c25527..4eee9078f --- a/src/main/target/CJMCU/hardware_revision.h +++ b/src/main/target/CJMCU/hardware_revision.h @@ -25,3 +25,5 @@ extern uint8_t hardwareRevision; void updateHardwareRevision(void); void detectHardwareRevision(void); + +void spiBusInit(void); diff --git a/src/main/target/COLIBRI_RACE/hardware_revision.c b/src/main/target/COLIBRI_RACE/hardware_revision.c new file mode 100755 index 000000000..2b7f3f7de --- /dev/null +++ b/src/main/target/COLIBRI_RACE/hardware_revision.c @@ -0,0 +1,60 @@ +/* + * This file is part of Cleanflight. + * + * Cleanflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Cleanflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Cleanflight. If not, see . + */ + +#include +#include +#include + +#include "platform.h" + +#include "build_config.h" + +#include "drivers/system.h" +#include "drivers/bus_spi.h" +#include "drivers/sensor.h" +#include "drivers/accgyro.h" +#include "drivers/accgyro_spi_mpu6500.h" + +#include "hardware_revision.h" + +void detectHardwareRevision(void) +{ +} + +void updateHardwareRevision(void) +{ +} + + +void spiBusInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHBPeriphClockCmd(MPU6500_CS_GPIO_CLK_PERIPHERAL, ENABLE); + + GPIO_InitStructure.GPIO_Pin = MPU6500_CS_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + GPIO_Init(MPU6500_CS_GPIO, &GPIO_InitStructure); + + GPIO_SetBits(MPU6500_CS_GPIO, MPU6500_CS_PIN); + + spiSetDivisor(MPU6500_SPI, SPI_9MHZ_CLOCK_DIVIDER); +} diff --git a/src/main/target/COLIBRI_RACE/hardware_revision.h b/src/main/target/COLIBRI_RACE/hardware_revision.h new file mode 100755 index 000000000..687e2eb0e --- /dev/null +++ b/src/main/target/COLIBRI_RACE/hardware_revision.h @@ -0,0 +1,21 @@ +/* + * This file is part of Cleanflight. + * + * Cleanflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Cleanflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Cleanflight. If not, see . + */ + + +void updateHardwareRevision(void); +void detectHardwareRevision(void); +void spiBusInit(void); diff --git a/src/main/target/COLIBRI_RACE/system_stm32f30x.c b/src/main/target/COLIBRI_RACE/system_stm32f30x.c new file mode 100755 index 000000000..fca696982 --- /dev/null +++ b/src/main/target/COLIBRI_RACE/system_stm32f30x.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.c + * @author MCD Application Team + * @version V1.1.1 + * @date 28-March-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F30x devices, + * and is generated by the clock configuration tool + * stm32f30x_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f30x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f30x.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F30x device + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 9 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * USB Clock | ENABLE + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 2 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** @addtogroup STM32F30x_System_Private_Includes + * @{ + */ + +#include "stm32f30x.h" + +uint32_t hse_value = HSE_VALUE; + +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ + +/** @addtogroup STM32F30x_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @addtogroup STM32F30x_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 72000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_FunctionPrototypes + * @{ + */ + +void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= (uint32_t)0xFF00FCCC; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + //SetSysClock(); // called from main() + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 2 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/main/target/COLIBRI_RACE/system_stm32f30x.h b/src/main/target/COLIBRI_RACE/system_stm32f30x.h new file mode 100755 index 000000000..4f999d305 --- /dev/null +++ b/src/main/target/COLIBRI_RACE/system_stm32f30x.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.h + * @author MCD Application Team + * @version V1.1.1 + * @date 28-March-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F30X_H +#define __SYSTEM_STM32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup STM32F30x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F30X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/main/target/COLIBRI_RACE/target.h b/src/main/target/COLIBRI_RACE/target.h new file mode 100755 index 000000000..7a6e5372d --- /dev/null +++ b/src/main/target/COLIBRI_RACE/target.h @@ -0,0 +1,168 @@ +/* + * This file is part of Cleanflight. + * + * Cleanflight is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * Cleanflight is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Cleanflight. If not, see . + */ + +#pragma once + +#define TARGET_BOARD_IDENTIFIER "CLBR" +#define USE_HARDWARE_REVISION_DETECTION + +#define LED0_GPIO GPIOC +#define LED0_PIN Pin_15 +#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOC + +#define LED1_GPIO GPIOC +#define LED1_PIN Pin_14 +#define LED1_PERIPHERAL RCC_AHBPeriph_GPIOC + +#define LED2_GPIO GPIOC +#define LED2_PIN Pin_13 +#define LED2_PERIPHERAL RCC_AHBPeriph_GPIOC + +#define BEEP_GPIO GPIOB +#define BEEP_PIN Pin_13 +#define BEEP_PERIPHERAL RCC_AHBPeriph_GPIOB +#define BEEPER_INVERTED + +#define MPU6500_SPI SPI1 +#define MPU6500_CS_GPIO_CLK_PERIPHERAL RCC_AHBPeriph_GPIOA +#define MPU6500_CS_GPIO GPIOA +#define MPU6500_CS_PIN GPIO_Pin_4 +#define MPU6500_SPI_INSTANCE SPI1 + +#define USE_SPI +#define USE_SPI_DEVICE_1 + +#define SPI1_GPIO GPIOB +#define SPI1_GPIO_PERIPHERAL RCC_AHBPeriph_GPIOB +#define SPI1_SCK_PIN GPIO_Pin_3 +#define SPI1_SCK_PIN_SOURCE GPIO_PinSource3 +#define SPI1_SCK_CLK RCC_AHBPeriph_GPIOB +#define SPI1_MISO_PIN GPIO_Pin_4 +#define SPI1_MISO_PIN_SOURCE GPIO_PinSource4 +#define SPI1_MISO_CLK RCC_AHBPeriph_GPIOB +#define SPI1_MOSI_PIN GPIO_Pin_5 +#define SPI1_MOSI_PIN_SOURCE GPIO_PinSource5 +#define SPI1_MOSI_CLK RCC_AHBPeriph_GPIOB + +#define USABLE_TIMER_CHANNEL_COUNT 11 + +#define GYRO +#define USE_GYRO_SPI_MPU6500 +#define GYRO_SPI_MPU6500_ALIGN CW270_DEG + +#define ACC +#define USE_ACC_SPI_MPU6500 +#define ACC_SPI_MPU6500_ALIGN CW270_DEG + +#define BARO +#define USE_BARO_MS5611 + +#define MAG +#define USE_MAG_HMC5883 +#define USE_MAG_AK8975 +//#define MAG_AK8975_ALIGN CW0_DEG_FLIP + +#define BEEPER +#define LED0 +#define LED1 +#define LED2 + +#define USE_VCP +#define USE_USART1 +#define USE_USART2 +#define USE_USART3 +#define SERIAL_PORT_COUNT 4 + +#define UART1_TX_PIN GPIO_Pin_4 +#define UART1_RX_PIN GPIO_Pin_5 +#define UART1_GPIO GPIOC +#define UART1_GPIO_AF GPIO_AF_7 +#define UART1_TX_PINSOURCE GPIO_PinSource4 +#define UART1_RX_PINSOURCE GPIO_PinSource5 + +#define UART2_TX_PIN GPIO_Pin_14 +#define UART2_RX_PIN GPIO_Pin_15 +#define UART2_GPIO GPIOA +#define UART2_GPIO_AF GPIO_AF_7 +#define UART2_TX_PINSOURCE GPIO_PinSource14 +#define UART2_RX_PINSOURCE GPIO_PinSource15 + +#define UART3_TX_PIN GPIO_Pin_10 +#define UART3_RX_PIN GPIO_Pin_11 +#define UART3_GPIO GPIOB +#define UART3_GPIO_AF GPIO_AF_7 +#define UART3_TX_PINSOURCE GPIO_PinSource10 +#define UART3_RX_PINSOURCE GPIO_PinSource11 + +#define USE_I2C +#define I2C_DEVICE (I2CDEV_2) + +#define I2C2_SCL_GPIO GPIOA +#define I2C2_SCL_GPIO_AF GPIO_AF_4 +#define I2C2_SCL_PIN GPIO_Pin_9 +#define I2C2_SCL_PIN_SOURCE GPIO_PinSource9 +#define I2C2_SCL_CLK_SOURCE RCC_AHBPeriph_GPIOA +#define I2C2_SDA_GPIO GPIOA +#define I2C2_SDA_GPIO_AF GPIO_AF_4 +#define I2C2_SDA_PIN GPIO_Pin_10 +#define I2C2_SDA_PIN_SOURCE GPIO_PinSource10 +#define I2C2_SDA_CLK_SOURCE RCC_AHBPeriph_GPIOA + +#define USE_ADC + +#define ADC_INSTANCE ADC1 +#define ADC_AHB_PERIPHERAL RCC_AHBPeriph_DMA1 +#define ADC_DMA_CHANNEL DMA1_Channel1 + +#define VBAT_ADC_GPIO GPIOC +#define VBAT_ADC_GPIO_PIN GPIO_Pin_0 +#define VBAT_ADC_CHANNEL ADC_Channel_6 + +#define CURRENT_METER_ADC_GPIO GPIOC +#define CURRENT_METER_ADC_GPIO_PIN GPIO_Pin_1 +#define CURRENT_METER_ADC_CHANNEL ADC_Channel_7 + +#define RSSI_ADC_GPIO GPIOC +#define RSSI_ADC_GPIO_PIN GPIO_Pin_2 +#define RSSI_ADC_CHANNEL ADC_Channel_8 + +#define EXTERNAL1_ADC_GPIO GPIOC +#define EXTERNAL1_ADC_GPIO_PIN GPIO_Pin_3 +#define EXTERNAL1_ADC_CHANNEL ADC_Channel_9 + +#define BLACKBOX +#define GPS +#define LED_STRIP + +#define LED_STRIP_TIMER TIM16 + +#define USE_LED_STRIP_ON_DMA1_CHANNEL3 +#define WS2811_GPIO GPIOA +#define WS2811_GPIO_AHB_PERIPHERAL RCC_AHBPeriph_GPIOA +#define WS2811_GPIO_AF GPIO_AF_1 +#define WS2811_PIN GPIO_Pin_6 // TIM16_CH1 +#define WS2811_PIN_SOURCE GPIO_PinSource6 +#define WS2811_TIMER TIM16 +#define WS2811_TIMER_APB2_PERIPHERAL RCC_APB2Periph_TIM16 +#define WS2811_DMA_CHANNEL DMA1_Channel3 +#define WS2811_IRQ DMA1_Channel3_IRQn + +#define TELEMETRY +#define SERIAL_RX +#define AUTOTUNE +#define USE_SERVOS +#define USE_CLI diff --git a/src/main/target/NAZE/hardware_revision.c b/src/main/target/NAZE/hardware_revision.c old mode 100644 new mode 100755 index 94c6404ce..fca6d6e55 --- a/src/main/target/NAZE/hardware_revision.c +++ b/src/main/target/NAZE/hardware_revision.c @@ -101,3 +101,7 @@ void updateHardwareRevision(void) hardwareRevision = NAZE32_SP; #endif } + +void spiBusInit(void) +{ +} diff --git a/src/main/target/NAZE/hardware_revision.h b/src/main/target/NAZE/hardware_revision.h old mode 100644 new mode 100755 index 09b1eeb90..9f663bb6c --- a/src/main/target/NAZE/hardware_revision.h +++ b/src/main/target/NAZE/hardware_revision.h @@ -26,3 +26,5 @@ extern uint8_t hardwareRevision; void updateHardwareRevision(void); void detectHardwareRevision(void); + +void spiBusInit(void);