hardfault handler w/ debugging info and an automatic breakpoint
This commit is contained in:
nathan
parent
1031e40a52
commit
46a49f6147
17
Makefile
17
Makefile
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@ -28,6 +28,10 @@ OPBL ?=no
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# Debugger optons, must be empty or GDB
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# Debugger optons, must be empty or GDB
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DEBUG ?=
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DEBUG ?=
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# Insert the debugging hardfault debugger
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# releases should not be built with this flag as it does not disable pwm output
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DEBUG_HARDFAULTS ?=
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# Serial port/Device for flashing
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# Serial port/Device for flashing
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SERIAL_DEVICE ?= $(firstword $(wildcard /dev/ttyUSB*) no-port-found)
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SERIAL_DEVICE ?= $(firstword $(wildcard /dev/ttyUSB*) no-port-found)
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@ -56,6 +60,13 @@ OPBL_VALID_TARGETS = CC3D_OPBL
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F3_TARGETS = STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO SPRACINGF3MINI SPRACINGF3EVO DOGE
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F3_TARGETS = STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO SPRACINGF3 IRCFUSIONF3 SPARKY ALIENFLIGHTF3 COLIBRI_RACE LUX_RACE MOTOLAB RMDO SPRACINGF3MINI SPRACINGF3EVO DOGE
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# note that there is no hardfault debugging startup file assembly handler for other platforms
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ifeq ($(DEBUG_HARDFAULTS),F3)
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CFLAGS += -DDEBUG_HARDFAULTS
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STM32F30x_COMMON_SRC = startup_stm32f3_debug_hardfault_handler.S
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else
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STM32F30x_COMMON_SRC = startup_stm32f30x_md_gcc.S
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endif
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# Configure default flash sizes for the targets
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# Configure default flash sizes for the targets
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ifeq ($(FLASH_SIZE),)
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ifeq ($(FLASH_SIZE),)
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@ -534,8 +545,8 @@ CC3D_SRC = \
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$(COMMON_SRC) \
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$(COMMON_SRC) \
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$(VCP_SRC)
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$(VCP_SRC)
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STM32F30x_COMMON_SRC = \
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startup_stm32f30x_md_gcc.S \
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STM32F30x_COMMON_SRC += \
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drivers/adc.c \
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drivers/adc.c \
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drivers/adc_stm32f30x.c \
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drivers/adc_stm32f30x.c \
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drivers/bus_i2c_stm32f30x.c \
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drivers/bus_i2c_stm32f30x.c \
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@ -816,7 +827,7 @@ endif
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DEBUG_FLAGS = -ggdb3 -DDEBUG
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DEBUG_FLAGS = -ggdb3 -DDEBUG
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CFLAGS = $(ARCH_FLAGS) \
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CFLAGS += $(ARCH_FLAGS) \
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$(LTO_FLAGS) \
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$(LTO_FLAGS) \
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$(addprefix -D,$(OPTIONS)) \
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$(addprefix -D,$(OPTIONS)) \
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$(addprefix -I,$(INCLUDE_DIRS)) \
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$(addprefix -I,$(INCLUDE_DIRS)) \
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@ -736,6 +736,66 @@ int main(void) {
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}
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}
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}
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}
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#ifdef DEBUG_HARDFAULTS
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//from: https://mcuoneclipse.com/2012/11/24/debugging-hard-faults-on-arm-cortex-m/
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/**
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* hard_fault_handler_c:
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* This is called from the HardFault_HandlerAsm with a pointer the Fault stack
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* as the parameter. We can then read the values from the stack and place them
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* into local variables for ease of reading.
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* We then read the various Fault Status and Address Registers to help decode
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* cause of the fault.
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* The function ends with a BKPT instruction to force control back into the debugger
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*/
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void hard_fault_handler_c(unsigned long *hardfault_args){
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volatile unsigned long stacked_r0 ;
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volatile unsigned long stacked_r1 ;
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volatile unsigned long stacked_r2 ;
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volatile unsigned long stacked_r3 ;
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volatile unsigned long stacked_r12 ;
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volatile unsigned long stacked_lr ;
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volatile unsigned long stacked_pc ;
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volatile unsigned long stacked_psr ;
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volatile unsigned long _CFSR ;
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volatile unsigned long _HFSR ;
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volatile unsigned long _DFSR ;
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volatile unsigned long _AFSR ;
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volatile unsigned long _BFAR ;
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volatile unsigned long _MMAR ;
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stacked_r0 = ((unsigned long)hardfault_args[0]) ;
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stacked_r1 = ((unsigned long)hardfault_args[1]) ;
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stacked_r2 = ((unsigned long)hardfault_args[2]) ;
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stacked_r3 = ((unsigned long)hardfault_args[3]) ;
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stacked_r12 = ((unsigned long)hardfault_args[4]) ;
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stacked_lr = ((unsigned long)hardfault_args[5]) ;
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stacked_pc = ((unsigned long)hardfault_args[6]) ;
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stacked_psr = ((unsigned long)hardfault_args[7]) ;
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// Configurable Fault Status Register
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// Consists of MMSR, BFSR and UFSR
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_CFSR = (*((volatile unsigned long *)(0xE000ED28))) ;
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// Hard Fault Status Register
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_HFSR = (*((volatile unsigned long *)(0xE000ED2C))) ;
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// Debug Fault Status Register
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_DFSR = (*((volatile unsigned long *)(0xE000ED30))) ;
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// Auxiliary Fault Status Register
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_AFSR = (*((volatile unsigned long *)(0xE000ED3C))) ;
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// Read the Fault Address Registers. These may not contain valid values.
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// Check BFARVALID/MMARVALID to see if they are valid values
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// MemManage Fault Address Register
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_MMAR = (*((volatile unsigned long *)(0xE000ED34))) ;
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// Bus Fault Address Register
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_BFAR = (*((volatile unsigned long *)(0xE000ED38))) ;
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__asm("BKPT #0\n") ; // Break into the debugger
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}
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#else
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void HardFault_Handler(void)
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void HardFault_Handler(void)
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{
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{
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// fall out of the sky
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// fall out of the sky
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@ -753,3 +813,4 @@ void HardFault_Handler(void)
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while (1);
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while (1);
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}
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}
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#endif
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@ -0,0 +1,501 @@
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/**
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******************************************************************************
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* @file startup_stm32f30x.s
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* @author MCD Application Team
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* @version V1.0.0
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* @date 04-Spetember-2012
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* @brief STM32F30x Devices vector table for RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the clock system and the external SRAM mounted on
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* STM3230C-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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.global HardFault_Handler
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.extern hard_fault_handler_c
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =0x20009FFC // HJI 11/9/2012
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ldr r1, =0xDEADBEEF // HJI 11/9/2012
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ldr r2, [r0, #0] // HJI 11/9/2012
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str r0, [r0, #0] // HJI 11/9/2012
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cmp r2, r1 // HJI 11/9/2012
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beq Reboot_Loader // HJI 11/9/2012
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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bx lr
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LoopForever:
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b LoopForever
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Reboot_Loader: // HJI 11/9/2012
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// Reboot to ROM // HJI 11/9/2012
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ldr r0, =0x1FFFD800 // HJI 4/26/2013
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ldr sp,[r0, #0] // HJI 11/9/2012
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ldr r0,[r0, #4] // HJI 11/9/2012
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bx r0 // HJI 11/9/2012
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.size Reset_Handler, .-Reset_Handler
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.section .text.Reset_Handler
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.weak HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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movs r0,#4
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movs r1, lr
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tst r0, r1
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beq _MSP
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mrs r0, psp
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b _HALT
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_MSP:
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mrs r0, msp
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_HALT:
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ldr r1,[r0,#20]
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b hard_fault_handler_c
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bkpt #0
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.size HardFault_Handler, .-HardFault_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M4. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word TAMPER_STAMP_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_TS_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word DMA1_Channel5_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_2_IRQHandler
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.word USB_HP_CAN1_TX_IRQHandler
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.word USB_LP_CAN1_RX0_IRQHandler
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.word CAN1_RX1_IRQHandler
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.word CAN1_SCE_IRQHandler
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.word EXTI9_5_IRQHandler
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.word TIM1_BRK_TIM15_IRQHandler
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.word TIM1_UP_TIM16_IRQHandler
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.word TIM1_TRG_COM_TIM17_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word TIM4_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word I2C2_EV_IRQHandler
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.word I2C2_ER_IRQHandler
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word USART1_IRQHandler
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.word USART2_IRQHandler
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.word USART3_IRQHandler
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.word EXTI15_10_IRQHandler
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.word RTC_Alarm_IRQHandler
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.word USBWakeUp_IRQHandler
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.word TIM8_BRK_IRQHandler
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.word TIM8_UP_IRQHandler
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.word TIM8_TRG_COM_IRQHandler
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.word TIM8_CC_IRQHandler
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.word ADC3_IRQHandler
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.word 0
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.word 0
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.word 0
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.word SPI3_IRQHandler
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.word UART4_IRQHandler
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.word UART5_IRQHandler
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.word TIM6_DAC_IRQHandler
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.word TIM7_IRQHandler
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.word DMA2_Channel1_IRQHandler
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.word DMA2_Channel2_IRQHandler
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.word DMA2_Channel3_IRQHandler
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.word DMA2_Channel4_IRQHandler
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.word DMA2_Channel5_IRQHandler
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|
.word ADC4_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word COMP1_2_3_IRQHandler
|
||||||
|
.word COMP4_5_6_IRQHandler
|
||||||
|
.word COMP7_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word USB_HP_IRQHandler
|
||||||
|
.word USB_LP_IRQHandler
|
||||||
|
.word USBWakeUp_RMP_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word FPU_IRQHandler
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_TS_IRQHandler
|
||||||
|
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC4_IRQHandler
|
||||||
|
.thumb_set ADC4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP1_2_3_IRQHandler
|
||||||
|
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP4_5_6_IRQHandler
|
||||||
|
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP7_IRQHandler
|
||||||
|
.thumb_set COMP7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_IRQHandler
|
||||||
|
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_IRQHandler
|
||||||
|
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_RMP_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
Loading…
Reference in New Issue