Merge pull request #7169 from jflyper/bfdev-fix-f411-clock-levels

[F411,SYSTEM] Delete bogus clock PLL parameter table entry
2018-12-04 20:46:23 +13:00 · 2018-12-04 20:46:23 +13:00 · 46fa249f25
parent b6408b3a32 ac02ee4cf2
commit 46fa249f25
1 changed files with 0 additions and 1 deletions
--- a/src/main/target/system_stm32f4xx.c
+++ b/src/main/target/system_stm32f4xx.c
@ -440,7 +440,6 @@ static const pllConfig_t overclockLevels[] = {
  { 216, 432, 2,  9 },  // 216 MHz
  { 240, 480, 2,  10 }  // 240 MHz
 #elif defined(STM32F411xE)
-  {  84, 336, 4,  7 },  // 84 MHz
  {  96, 384, 4,  8 },  // 96 MHz
  { 108, 432, 4,  9 },  // 108 MHz
  { 120, 480, 4, 10 },  // 120 MHz