commit
4b01b9d4d9
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@ -269,11 +269,11 @@ void init(void)
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#if defined(STM32F4) && !defined(DISABLE_OVERCLOCK)
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#if defined(STM32F4) && !defined(DISABLE_OVERCLOCK)
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// If F4 Overclocking is set and System core clock is not correct a reset is forced
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// If F4 Overclocking is set and System core clock is not correct a reset is forced
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if (systemConfig()->cpu_overclock && SystemCoreClock != 240000000) {
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if (systemConfig()->cpu_overclock && SystemCoreClock != 240000000) {
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*((uint32_t *)0x2001FFFC) = 0xDEADBABE; // 128KB SRAM STM32F4XX
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*((uint32_t *)0x2001FFF8) = 0xDEADBABE; // 128KB SRAM STM32F4XX
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__disable_irq();
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__disable_irq();
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NVIC_SystemReset();
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NVIC_SystemReset();
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} else if (!systemConfig()->cpu_overclock && SystemCoreClock == 240000000) {
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} else if (!systemConfig()->cpu_overclock && SystemCoreClock == 240000000) {
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*((uint32_t *)0x2001FFFC) = 0x0; // 128KB SRAM STM32F4XX
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*((uint32_t *)0x2001FFF8) = 0x0; // 128KB SRAM STM32F4XX
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__disable_irq();
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__disable_irq();
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NVIC_SystemReset();
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NVIC_SystemReset();
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}
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}
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@ -79,14 +79,6 @@ Reset_Handler:
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str r1, [r0, #0x30]
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str r1, [r0, #0x30]
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dsb
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dsb
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// Check for overclocking request
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ldr r0, =0x2001FFFC // Faduf
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ldr r1, =0xDEADBABE // Faduf
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ldr r2, [r0, #0] // Faduf
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str r0, [r0, #0] // Faduf
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cmp r2, r1 // Faduf
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beq Boot_OC // Faduf
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// Check for bootloader reboot
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// Check for bootloader reboot
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ldr r0, =0x2001FFFC // mj666
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ldr r0, =0x2001FFFC // mj666
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ldr r1, =0xDEADBEEF // mj666
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ldr r1, =0xDEADBEEF // mj666
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@ -95,6 +87,14 @@ Reset_Handler:
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cmp r2, r1 // mj666
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cmp r2, r1 // mj666
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beq Reboot_Loader // mj666
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beq Reboot_Loader // mj666
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// Check for overclocking request
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ldr r0, =0x2001FFF8 // Faduf
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ldr r1, =0xDEADBABE // Faduf
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ldr r2, [r0, #0] // Faduf
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str r0, [r0, #0] // Faduf
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cmp r2, r1 // Faduf
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beq Boot_OC // Faduf
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/* Copy the data segment initializers from flash to SRAM */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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movs r1, #0
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b LoopCopyDataInit
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b LoopCopyDataInit
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