added overclock feature
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parent
03fab3f915
commit
6716ecfe7e
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@ -1,3 +1,4 @@
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#include <stdbool.h>
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#include "stm32f10x.h"
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#define SYSCLK_FREQ_72MHz 72000000
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@ -86,7 +87,7 @@ enum {
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};
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// Set system clock to 72 (HSE) or 64 (HSI) MHz
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void SetSysClock(void)
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void SetSysClock(bool overclock)
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{
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__IO uint32_t StartUpCounter = 0, status = 0, clocksrc = SRC_NONE;
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__IO uint32_t *RCC_CRH = &GPIOC->CRH;
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@ -140,10 +141,18 @@ void SetSysClock(void)
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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*RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
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GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
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RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
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switch (clocksrc) {
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case SRC_HSE:
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// PLL configuration: PLLCLK = HSE * 9 = 72 MHz
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if (overclock) {
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if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL6)
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RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL7;
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else if (RCC_CFGR_PLLMUL == RCC_CFGR_PLLMULL9)
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RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL10;
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}
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// overclock=false : PLL configuration: PLLCLK = HSE * 9 = 72 MHz || HSE * 6 = 72 MHz
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// overclock=true : PLL configuration: PLLCLK = HSE * 10 = 80 MHz || HSE * 7 = 84 MHz
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL);
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break;
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case SRC_HSI:
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@ -75,6 +75,7 @@ typedef enum {
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FEATURE_POWERMETER = 1 << 12,
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FEATURE_VARIO = 1 << 13,
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FEATURE_3D = 1 << 14,
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FEATURE_OVERCLOCK = 1 << 15,
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} AvailableFeatures;
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typedef enum {
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@ -54,7 +54,7 @@ static const char * const mixerNames[] = {
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static const char * const featureNames[] = {
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"PPM", "VBAT", "INFLIGHT_ACC_CAL", "SERIALRX", "MOTOR_STOP",
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"SERVO_TILT", "SOFTSERIAL", "LED_RING", "GPS",
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"FAILSAFE", "SONAR", "TELEMETRY", "POWERMETER", "VARIO", "3D",
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"FAILSAFE", "SONAR", "TELEMETRY", "POWERMETER", "VARIO", "3D", "OVERCLOCK",
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NULL
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};
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16
src/config.c
16
src/config.c
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@ -56,8 +56,6 @@ static uint8_t validEEPROM(void)
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void readEEPROM(void)
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{
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uint8_t i;
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// Sanity check
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if (!validEEPROM())
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failureMode(10);
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@ -67,8 +65,12 @@ void readEEPROM(void)
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// Copy current profile
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if (mcfg.current_profile > 2) // sanity check
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mcfg.current_profile = 0;
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memcpy(&cfg, &mcfg.profile[mcfg.current_profile], sizeof(config_t));
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memcpy(&cfg, &mcfg.profile[mcfg.current_profile], sizeof(config_t));
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}
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void activateConfig(void)
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{
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uint8_t i;
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for (i = 0; i < PITCH_LOOKUP_LENGTH; i++)
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lookupPitchRollRC[i] = (2500 + cfg.rcExpo8 * (i * i - 25)) * i * (int32_t) cfg.rcRate8 / 2500;
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@ -87,6 +89,12 @@ void readEEPROM(void)
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gpsSetPIDs();
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}
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void loadAndActivateConfig(void)
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{
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readEEPROM();
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activateConfig();
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}
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void writeEEPROM(uint8_t b, uint8_t updateProfile)
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{
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FLASH_Status status;
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@ -139,7 +147,7 @@ retry:
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}
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// re-read written data
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readEEPROM();
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loadAndActivateConfig();
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if (b)
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blinkLED(15, 20, 1);
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}
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@ -5,7 +5,9 @@ static volatile uint32_t usTicks = 0;
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// current uptime for 1kHz systick timer. will rollover after 49 days. hopefully we won't care.
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static volatile uint32_t sysTickUptime = 0;
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// from system_stm32f10x.c
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void SetSysClock(void);
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void SetSysClock(bool overclock);
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// from config.h
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bool feature(uint32_t mask);
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#ifdef BUZZER
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void systemBeep(bool onoff);
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static void beepRev4(bool onoff);
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@ -75,7 +77,7 @@ void systemInit(void)
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// Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
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// Configure the Flash Latency cycles and enable prefetch buffer
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SetSysClock();
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SetSysClock(feature(FEATURE_OVERCLOCK));
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// Turn on clocks for stuff we use
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4 | RCC_APB1Periph_I2C2, ENABLE);
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@ -36,13 +36,14 @@ int main(void)
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serialPort_t* loopbackPort1 = NULL;
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serialPort_t* loopbackPort2 = NULL;
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#endif
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checkFirstTime(false);
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readEEPROM();
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systemInit();
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#ifdef USE_LAME_PRINTF
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init_printf(NULL, _putc);
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#endif
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checkFirstTime(false);
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readEEPROM();
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activateConfig();
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// configure power ADC
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if (mcfg.power_adc_channel > 0 && (mcfg.power_adc_channel == 1 || mcfg.power_adc_channel == 9))
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