F446 support
This commit is contained in:
jflyper
parent
f6c7003ab1
commit
67b9966dc6
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@ -1018,7 +1018,7 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
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/* Check the parameters */
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/* Check the parameters */
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assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
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assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F446xx)
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if (PWR_FLAG != PWR_FLAG_UDRDY)
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if (PWR_FLAG != PWR_FLAG_UDRDY)
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{
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{
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PWR->CR |= PWR_FLAG << 2;
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PWR->CR |= PWR_FLAG << 2;
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@ -82,7 +82,7 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
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uint32_t timerClock(TIM_TypeDef *tim)
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uint32_t timerClock(TIM_TypeDef *tim)
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{
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{
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#if defined (STM32F411xE)
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#if defined (STM32F411xE) || defined (STM32F446xx)
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UNUSED(tim);
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UNUSED(tim);
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return SystemCoreClock;
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return SystemCoreClock;
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#elif defined (STM32F40_41xxx)
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#elif defined (STM32F40_41xxx)
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@ -0,0 +1,490 @@
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/**
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******************************************************************************
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* @file startup_stm32f40_41xxx.s
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* @author MCD Application Team
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* @version V1.6.1
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* @date 21-October-2015
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* @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain.
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* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Configure the clock system and the external SRAM mounted on
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* STM324xG-EVAL board to be used as data memory (optional,
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* to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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// Enable CCM
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// RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN;
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ldr r0, =0x40023800 // RCC_BASE
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ldr r1, [r0, #0x30] // AHB1ENR
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orr r1, r1, 0x00100000 // RCC_AHB1ENR_CCMDATARAMEN
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str r1, [r0, #0x30]
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dsb
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// Check for bootloader reboot
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ldr r0, =0x2001FFFC // mj666
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ldr r1, =0xDEADBEEF // mj666
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ldr r2, [r0, #0] // mj666
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str r0, [r0, #0] // mj666
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cmp r2, r1 // mj666
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beq Reboot_Loader // mj666
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Mark the heap and stack */
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ldr r2, =_heap_stack_begin
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b LoopMarkHeapStack
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MarkHeapStack:
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movs r3, 0xa5a5a5a5
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str r3, [r2], #4
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LoopMarkHeapStack:
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ldr r3, = _heap_stack_end
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cmp r2, r3
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bcc MarkHeapStack
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/*FPU settings*/
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ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
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ldr r1,[r0]
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orr r1,r1,#(0xF << 20)
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str r1,[r0]
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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bx lr
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LoopForever:
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b LoopForever
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Reboot_Loader: // mj666
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// Reboot to ROM // mj666
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ldr r0, =0x1FFF0000 // mj666
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ldr sp,[r0, #0] // mj666
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ldr r0,[r0, #4] // mj666
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bx r0 // mj666
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M4. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_IRQHandler /* PVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word 0 /* CAN1 TX */
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.word 0 /* CAN1 RX0 */
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.word 0 /* CAN1 RX1 */
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.word 0 /* CAN1 SCE */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word 0 /* USART3 */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.word 0 /* TIM8 Break and TIM12 */
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.word 0 /* TIM8 Update and TIM13 */
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.word 0 /* TIM8 Trigger and Commutation and TIM14 */
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.word 0 /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word 0 /* FSMC */
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.word SDIO_IRQHandler /* SDIO */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word 0 /* UART4 */
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.word 0 /* UART5 */
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.word 0 /* TIM6 and DAC1&2 underrun errors */
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.word 0 /* TIM7 */
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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.word 0 /* Ethernet */
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.word 0 /* Ethernet Wakeup through EXTI line */
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.word 0 /* CAN2 TX */
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.word 0 /* CAN2 RX0 */
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.word 0 /* CAN2 RX1 */
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.word 0 /* CAN2 SCE */
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.word OTG_FS_IRQHandler /* USB OTG FS */
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.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
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.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
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.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
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.word USART6_IRQHandler /* USART6 */
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.word I2C3_EV_IRQHandler /* I2C3 event */
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.word I2C3_ER_IRQHandler /* I2C3 error */
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.word 0 /* USB OTG HS End Point 1 Out */
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.word 0 /* USB OTG HS End Point 1 In */
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.word 0 /* USB OTG HS Wakeup through EXTI */
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.word 0 /* USB OTG HS */
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.word 0 /* DCMI */
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.word 0 /* CRYP crypto */
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.word 0 /* Hash and Rng */
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.word FPU_IRQHandler /* FPU */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word SPI4_IRQHandler /* SPI4 */
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.word SPI5_IRQHandler /* SPI5 */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_IRQHandler
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.thumb_set PVD_IRQHandler,Default_Handler
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.weak TAMP_STAMP_IRQHandler
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.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
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.weak RTC_WKUP_IRQHandler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM9_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM10_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* This file is part of Cleanflight.
|
||||||
|
*
|
||||||
|
* Cleanflight is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* Cleanflight is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform.h>
|
||||||
|
|
||||||
|
#ifdef USE_TARGET_CONFIG
|
||||||
|
|
||||||
|
|
||||||
|
#include "io/serial.h"
|
||||||
|
|
||||||
|
|
||||||
|
void targetConfiguration(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
serialConfigMutable()->portConfigs[0].functionMask = FUNCTION_MSP;
|
||||||
|
serialConfigMutable()->portConfigs[1].functionMask = FUNCTION_MSP;
|
||||||
|
serialConfigMutable()->portConfigs[2].functionMask = FUNCTION_MSP;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* This file is part of Cleanflight.
|
||||||
|
*
|
||||||
|
* Cleanflight is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* Cleanflight is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <platform.h>
|
||||||
|
#include "drivers/io.h"
|
||||||
|
|
||||||
|
#include "drivers/timer.h"
|
||||||
|
#include "drivers/timer_def.h"
|
||||||
|
#include "drivers/dma.h"
|
||||||
|
|
||||||
|
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
|
||||||
|
DEF_TIM(TIM1, CH1, PA8, TIM_USE_MOTOR, 0, 1),
|
||||||
|
DEF_TIM(TIM8, CH1, PC6, TIM_USE_MOTOR, 0, 1),
|
||||||
|
DEF_TIM(TIM8, CH2, PC7, TIM_USE_MOTOR, 0, 1),
|
||||||
|
DEF_TIM(TIM8, CH3, PC8, TIM_USE_MOTOR, 0, 1),
|
||||||
|
DEF_TIM(TIM3, CH4, PB1, 0, 0, 0),
|
||||||
|
DEF_TIM(TIM3, CH2, PA4, 0, 0, 0),
|
||||||
|
DEF_TIM(TIM2, CH2, PA1, 0, 0, 0),
|
||||||
|
DEF_TIM(TIM2, CH3, PA2, 0, 0, 0)
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,153 @@
|
||||||
|
/*
|
||||||
|
* This software is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This software is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this software. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#define USE_TARGET_CONFIG
|
||||||
|
|
||||||
|
#define TARGET_BOARD_IDENTIFIER "N446" // STM32 Nucleo F446RE
|
||||||
|
#define USBD_PRODUCT_STRING "NucleoF446RE"
|
||||||
|
|
||||||
|
#define LED0_PIN PA5 // Onboard LED
|
||||||
|
|
||||||
|
//#define BEEPER PD12
|
||||||
|
|
||||||
|
#define USE_EXTI
|
||||||
|
|
||||||
|
#define USE_SPI
|
||||||
|
//#define USE_SPI_DEVICE_1
|
||||||
|
#define USE_SPI_DEVICE_2
|
||||||
|
|
||||||
|
#define SPI2_NSS_PIN PB12
|
||||||
|
#define SPI2_SCK_PIN PB13
|
||||||
|
#define SPI2_MISO_PIN PB14
|
||||||
|
#define SPI2_MOSI_PIN PB15
|
||||||
|
|
||||||
|
#define USE_GYRO
|
||||||
|
#define USE_FAKE_GYRO
|
||||||
|
#define USE_GYRO_SPI_MPU6500
|
||||||
|
#define USE_GYRO_SPI_MPU9250
|
||||||
|
|
||||||
|
#define USE_ACC
|
||||||
|
#define USE_FAKE_ACC
|
||||||
|
#define USE_ACC_SPI_MPU6500
|
||||||
|
#define USE_ACC_SPI_MPU9250
|
||||||
|
|
||||||
|
#define MPU9250_CS_PIN PB12
|
||||||
|
#define MPU9250_SPI_INSTANCE SPI2
|
||||||
|
|
||||||
|
#define MPU6500_CS_PIN PB12
|
||||||
|
#define MPU6500_SPI_INSTANCE SPI2
|
||||||
|
|
||||||
|
#define USE_EXTI
|
||||||
|
|
||||||
|
//#define MPU_INT_EXTI PC13
|
||||||
|
//#define USE_MPU_DATA_READY_SIGNAL
|
||||||
|
//#define ENSURE_MPU_DATA_READY_IS_LOW
|
||||||
|
|
||||||
|
#define USE_BARO
|
||||||
|
#define USE_FAKE_BARO
|
||||||
|
//#define USE_BARO_BMP085
|
||||||
|
//#define USE_BARO_BMP280
|
||||||
|
//#define USE_BARO_MS5611
|
||||||
|
|
||||||
|
//#define OSD
|
||||||
|
//#define USE_MAX7456
|
||||||
|
//#define MAX7456_SPI_INSTANCE SPI2
|
||||||
|
//#define MAX7456_SPI_CS_PIN SPI2_NSS_PIN
|
||||||
|
|
||||||
|
#define CMS
|
||||||
|
|
||||||
|
//#define USE_SDCARD
|
||||||
|
//
|
||||||
|
//#define SDCARD_SPI_INSTANCE SPI2
|
||||||
|
//#define SDCARD_SPI_CS_PIN PB12
|
||||||
|
//// SPI2 is on the APB1 bus whose clock runs at 36MHz. Divide to under 400kHz for init:
|
||||||
|
//#define SDCARD_SPI_INITIALIZATION_CLOCK_DIVIDER 128
|
||||||
|
//// Divide to under 25MHz for normal operation:
|
||||||
|
//#define SDCARD_SPI_FULL_SPEED_CLOCK_DIVIDER 2
|
||||||
|
//
|
||||||
|
//// Note, this is the same DMA channel as UART1_RX. Luckily we don't use DMA for USART Rx.
|
||||||
|
//#define SDCARD_DMA_CHANNEL_TX DMA1_Channel5
|
||||||
|
//#define SDCARD_DMA_CHANNEL_TX_COMPLETE_FLAG DMA1_FLAG_TC5
|
||||||
|
|
||||||
|
// Performance logging for SD card operations:
|
||||||
|
// #define AFATFS_USE_INTROSPECTIVE_LOGGING
|
||||||
|
|
||||||
|
#define USE_MAG
|
||||||
|
#define USE_FAKE_MAG
|
||||||
|
//#define USE_MAG_AK8963
|
||||||
|
//#define USE_MAG_AK8975
|
||||||
|
//#define USE_MAG_HMC5883
|
||||||
|
|
||||||
|
#define USE_VCP
|
||||||
|
|
||||||
|
#define USE_UART1
|
||||||
|
#define UART1_TX_PIN PA9
|
||||||
|
#define UART1_RX_PIN PA10
|
||||||
|
|
||||||
|
#define USE_UART2
|
||||||
|
#define UART2_TX_PIN PA2
|
||||||
|
#define UART2_RX_PIN PA3
|
||||||
|
|
||||||
|
#define USE_UART3
|
||||||
|
#define UART3_TX_PIN PB10
|
||||||
|
#define UART3_RX_PIN PB11
|
||||||
|
|
||||||
|
//#define USE_UART4
|
||||||
|
//#define USE_UART5
|
||||||
|
|
||||||
|
#define USE_SOFTSERIAL1
|
||||||
|
#define USE_SOFTSERIAL2
|
||||||
|
|
||||||
|
#define SERIAL_PORT_COUNT 6
|
||||||
|
|
||||||
|
#define USE_ESCSERIAL
|
||||||
|
#define ESCSERIAL_TIMER_TX_PIN PB8 // (HARDARE=0,PPM)
|
||||||
|
#define USE_SERIAL_4WAY_BLHELI_INTERFACE
|
||||||
|
|
||||||
|
#define USE_I2C
|
||||||
|
|
||||||
|
#define USE_I2C_DEVICE_2
|
||||||
|
#define I2C2_SCL NONE // PB10, shared with UART3TX
|
||||||
|
#define I2C2_SDA NONE // PB11, shared with UART3RX
|
||||||
|
|
||||||
|
#define USE_I2C_DEVICE_3
|
||||||
|
#define I2C3_SCL NONE // PA8
|
||||||
|
#define I2C3_SDA NONE // PC9
|
||||||
|
#define I2C_DEVICE (I2CDEV_2)
|
||||||
|
|
||||||
|
#define USE_ADC
|
||||||
|
#define ADC_INSTANCE ADC1
|
||||||
|
#define VBAT_ADC_PIN PC0
|
||||||
|
#define CURRENT_METER_ADC_PIN PC1
|
||||||
|
#define RSSI_ADC_PIN PC2
|
||||||
|
#define EXTERNAL1_ADC_PIN PC3
|
||||||
|
|
||||||
|
#define USE_ESC_SENSOR
|
||||||
|
|
||||||
|
#define USE_SONAR
|
||||||
|
#define SONAR_TRIGGER_PIN PB0
|
||||||
|
#define SONAR_ECHO_PIN PB1
|
||||||
|
|
||||||
|
#define MAX_SUPPORTED_MOTORS 12
|
||||||
|
|
||||||
|
#define TARGET_IO_PORTA (0xffff & ~(BIT(14)|BIT(13)))
|
||||||
|
#define TARGET_IO_PORTB (0xffff & ~(BIT(2)))
|
||||||
|
#define TARGET_IO_PORTC (0xffff & ~(BIT(15)|BIT(14)|BIT(13)))
|
||||||
|
#define TARGET_IO_PORTD BIT(2)
|
||||||
|
|
||||||
|
#define USABLE_TIMER_CHANNEL_COUNT 12
|
||||||
|
#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(8) )
|
||||||
|
|
@ -0,0 +1,10 @@
|
||||||
|
F446_TARGETS += $(TARGET)
|
||||||
|
FEATURES = VCP
|
||||||
|
|
||||||
|
TARGET_SRC = \
|
||||||
|
drivers/accgyro/accgyro_mpu6500.c \
|
||||||
|
drivers/accgyro/accgyro_spi_mpu6500.c \
|
||||||
|
drivers/accgyro/accgyro_spi_mpu9250.c \
|
||||||
|
drivers/accgyro/accgyro_fake.c \
|
||||||
|
drivers/barometer/barometer_fake.c \
|
||||||
|
drivers/compass/compass_fake.c
|
||||||
|
|
@ -0,0 +1,43 @@
|
||||||
|
/*
|
||||||
|
* This file is part of Cleanflight.
|
||||||
|
*
|
||||||
|
* Cleanflight is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* Cleanflight is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <platform.h>
|
||||||
|
#include "drivers/io.h"
|
||||||
|
|
||||||
|
#include "drivers/timer.h"
|
||||||
|
#include "drivers/timer_def.h"
|
||||||
|
#include "drivers/dma.h"
|
||||||
|
|
||||||
|
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
|
||||||
|
DEF_TIM(TIM3, CH4, PB1, TIM_USE_MOTOR, 0, 0), // pin 27 - M1 - DMA1_ST2
|
||||||
|
DEF_TIM(TIM3, CH3, PB0, TIM_USE_MOTOR, 0, 0), // pin 26 - M2 - DMA1_ST7
|
||||||
|
DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 0, 0), // pin 57 - M3 - DMA1_ST5
|
||||||
|
DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 0, 0), // pin 56 - M4 - DMA1_ST4
|
||||||
|
DEF_TIM(TIM8, CH1, PC6, TIM_USE_LED, 0, 0), // LED_STRIP - DMA2_ST2
|
||||||
|
|
||||||
|
// Backdoor timers
|
||||||
|
DEF_TIM(TIM1, CH2, PA9, TIM_USE_NONE , 0, 0), // UART1_TX T1C2
|
||||||
|
DEF_TIM(TIM1, CH3, PA10, TIM_USE_NONE , 0, 0), // UART1_RX T1C3
|
||||||
|
|
||||||
|
DEF_TIM(TIM2, CH3, PA2, TIM_USE_NONE , 0, 0), // UART2_TX T5C3,T9C1,T2C3
|
||||||
|
DEF_TIM(TIM9, CH2, PA3, TIM_USE_NONE , 0, 0), // UART2_RX T5C4,T9C2,T2C4
|
||||||
|
|
||||||
|
DEF_TIM(TIM5, CH1, PA0, TIM_USE_NONE , 0, 0), // UART4_TX T5C1
|
||||||
|
DEF_TIM(TIM5, CH2, PA1, TIM_USE_NONE , 0, 0), // UART4_RX T5C2,T2C2
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,126 @@
|
||||||
|
/*
|
||||||
|
* This software is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This software is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this software. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#define TARGET_BOARD_IDENTIFIER "SKF4"
|
||||||
|
|
||||||
|
#define USBD_PRODUCT_STRING "SpektrumF400"
|
||||||
|
|
||||||
|
#define LED0_PIN PA15
|
||||||
|
#define LED1_PIN PC8
|
||||||
|
|
||||||
|
#define BEEPER PC2
|
||||||
|
#define BEEPER_INVERTED
|
||||||
|
|
||||||
|
#define USE_SPI
|
||||||
|
|
||||||
|
#define USE_SPI_DEVICE_1
|
||||||
|
#define SPI1_NSS_PIN PA4
|
||||||
|
#define SPI1_SCK_PIN PA5
|
||||||
|
#define SPI1_MISO_PIN PA6
|
||||||
|
#define SPI1_MOSI_PIN PA7
|
||||||
|
|
||||||
|
#define USE_SPI_DEVICE_2
|
||||||
|
#define SPI2_NSS_PIN PB12
|
||||||
|
#define SPI2_SCK_PIN PB13
|
||||||
|
#define SPI2_MISO_PIN PB14
|
||||||
|
#define SPI2_MOSI_PIN PB15
|
||||||
|
|
||||||
|
//#define USE_FLASHFS
|
||||||
|
//#define USE_FLASH_M25P16
|
||||||
|
|
||||||
|
//#define M25P16_CS_PIN PB12
|
||||||
|
//#define M25P16_SPI_INSTANCE SPI2
|
||||||
|
|
||||||
|
#define USE_GYRO
|
||||||
|
#define USE_GYRO_SPI_MPU6500
|
||||||
|
#define USE_GYRO_SPI_MPU9250
|
||||||
|
#define GYRO_MPU9250_ALIGN CW270_DEG
|
||||||
|
|
||||||
|
#define USE_ACC
|
||||||
|
#define USE_ACC_SPI_MPU6500
|
||||||
|
#define USE_ACC_SPI_MPU9250
|
||||||
|
#define ACC_MPU9250_ALIGN CW270_DEG
|
||||||
|
|
||||||
|
#define MPU9250_CS_PIN PB12
|
||||||
|
#define MPU9250_SPI_INSTANCE SPI2
|
||||||
|
|
||||||
|
#define MPU6500_CS_PIN PB12
|
||||||
|
#define MPU6500_SPI_INSTANCE SPI2
|
||||||
|
|
||||||
|
#define USE_EXTI
|
||||||
|
#define MPU_INT_EXTI PC13
|
||||||
|
#define USE_MPU_DATA_READY_SIGNAL
|
||||||
|
#define ENSURE_MPU_DATA_READY_IS_LOW
|
||||||
|
|
||||||
|
#define USE_VCP
|
||||||
|
|
||||||
|
#define USE_UART1
|
||||||
|
#define UART1_TX_PIN PA9
|
||||||
|
#define UART1_RX_PIN PA10
|
||||||
|
|
||||||
|
#define USE_UART2
|
||||||
|
#define UART2_TX_PIN PA2
|
||||||
|
#define UART2_RX_PIN PA3
|
||||||
|
|
||||||
|
#define USE_UART3
|
||||||
|
#define UART3_RX_PIN PC11
|
||||||
|
#define UART3_TX_PIN PC10
|
||||||
|
|
||||||
|
#define USE_UART4
|
||||||
|
#define UART4_RX_PIN PA1
|
||||||
|
#define UART4_TX_PIN PA0
|
||||||
|
|
||||||
|
#define USE_UART5
|
||||||
|
//#define UART5_RX_PIN PC12 // XXX ???
|
||||||
|
#define UART5_TX_PIN PC12
|
||||||
|
|
||||||
|
#define USE_SOFTSERIAL1
|
||||||
|
#define USE_SOFTSERIAL2
|
||||||
|
|
||||||
|
#define SERIAL_PORT_COUNT 8
|
||||||
|
|
||||||
|
#define USE_ESCSERIAL
|
||||||
|
#define ESCSERIAL_TIMER_TX_PIN PB8
|
||||||
|
|
||||||
|
#define USE_SERIAL_4WAY_BLHELI_INTERFACE
|
||||||
|
|
||||||
|
#define USE_I2C
|
||||||
|
|
||||||
|
#define USE_I2C_DEVICE_1
|
||||||
|
#define I2C1_SCL PB8
|
||||||
|
#define I2C1_SDA PB9
|
||||||
|
|
||||||
|
#define USE_I2C_DEVICE_2
|
||||||
|
#define I2C2_SCL NONE // PB10, Shared with UART3_TX
|
||||||
|
#define I2C2_SDA NONE // PB11, Shared with UART3_RX
|
||||||
|
|
||||||
|
#define I2C_DEVICE (I2CDEV_1)
|
||||||
|
|
||||||
|
#define USE_ADC
|
||||||
|
#define ADC_INSTANCE ADC1
|
||||||
|
#define VBAT_ADC_PIN PC0
|
||||||
|
#define CURRENT_METER_ADC_PIN PC3
|
||||||
|
|
||||||
|
#define TARGET_XTAL_MHZ 12
|
||||||
|
|
||||||
|
#define TARGET_IO_PORTA (0xffff & ~(BIT(14)|BIT(13)))
|
||||||
|
#define TARGET_IO_PORTB (0xffff & ~(BIT(2)))
|
||||||
|
#define TARGET_IO_PORTC 0xffff
|
||||||
|
#define TARGET_IO_PORTD BIT(2)
|
||||||
|
|
||||||
|
#define USABLE_TIMER_CHANNEL_COUNT 11
|
||||||
|
#define USED_TIMERS (TIM_N(1)|TIM_N(2)|TIM_N(3)|TIM_N(5)|TIM_N(8)|TIM_N(9))
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
F446_TARGETS += $(TARGET)
|
||||||
|
|
||||||
|
#FEATURES = VCP ONBOARDFLASH
|
||||||
|
FEATURES = VCP
|
||||||
|
|
||||||
|
HSE_VALUE = 12000000
|
||||||
|
|
||||||
|
TARGET_SRC = \
|
||||||
|
drivers/accgyro/accgyro_mpu6500.c \
|
||||||
|
drivers/accgyro/accgyro_spi_mpu6500.c \
|
||||||
|
drivers/accgyro/accgyro_spi_mpu9250.c
|
||||||
|
|
@ -504,10 +504,15 @@ void SystemInit(void)
|
||||||
|
|
||||||
void SystemInitOC(void)
|
void SystemInitOC(void)
|
||||||
{
|
{
|
||||||
|
#if !defined(STM32F446xxx)
|
||||||
|
// XXX Doesn't work for F446 with this configuration.
|
||||||
|
// XXX Need to use smaller M to reduce N?
|
||||||
|
|
||||||
/* PLL setting for overclocking */
|
/* PLL setting for overclocking */
|
||||||
pll_n = PLL_N_OC;
|
pll_n = PLL_N_OC;
|
||||||
pll_p = PLL_P_OC;
|
pll_p = PLL_P_OC;
|
||||||
pll_q = PLL_Q_OC;
|
pll_q = PLL_Q_OC;
|
||||||
|
#endif
|
||||||
|
|
||||||
SystemInit();
|
SystemInit();
|
||||||
}
|
}
|
||||||
|
|
@ -739,6 +744,44 @@ void SetSysClock(void)
|
||||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||||
configuration. User can add here some code to deal with this error */
|
configuration. User can add here some code to deal with this error */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(STM32F446xx)
|
||||||
|
// Always use PLLSAI to derive USB 48MHz clock.
|
||||||
|
// - This also works under arbitral overclocking situations.
|
||||||
|
// - Only handles HSE case.
|
||||||
|
|
||||||
|
#ifdef TARGET_XTAL_MHZ
|
||||||
|
#define PLLSAI_M TARGET_XTAL_MHZ
|
||||||
|
#else
|
||||||
|
#define PLLSAI_M 8
|
||||||
|
#endif
|
||||||
|
#define PLLSAI_N 192
|
||||||
|
#define PLLSAI_P 4
|
||||||
|
#define PLLSAI_Q 2
|
||||||
|
|
||||||
|
#define RCC_PLLSAI_IS_READY() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
|
||||||
|
|
||||||
|
/* Configure 48MHz clock for USB */
|
||||||
|
// Set 48MHz clock source
|
||||||
|
RCC_48MHzClockSourceConfig(RCC_48MHZCLKSource_PLLSAI);
|
||||||
|
|
||||||
|
// Enable PLLSAI
|
||||||
|
RCC_PLLSAICmd(DISABLE);
|
||||||
|
|
||||||
|
// wait for PLLSAI to be disabled
|
||||||
|
while (RCC_PLLSAI_IS_READY()) {}
|
||||||
|
|
||||||
|
RCC_PLLSAIConfig(PLLSAI_M, PLLSAI_N, PLLSAI_P, PLLSAI_Q);
|
||||||
|
|
||||||
|
RCC_PLLSAICmd(ENABLE);
|
||||||
|
|
||||||
|
// wait for PLLSAI to be enabled
|
||||||
|
while (!RCC_PLLSAI_IS_READY()) {}
|
||||||
|
|
||||||
|
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
|
||||||
|
|
||||||
|
#undef RCC_PLLSAI_GET_FLAG
|
||||||
|
#endif /* STM32F446xx */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue