Merge pull request #9494 from jflyper/bfdev-rcc_clock_cmd-for-hal
Support RCC_ClockCmd and RCC_ResetCmd for HAL
This commit is contained in:
commit
6b43827f55
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@ -433,11 +433,13 @@ void adcInit(const adcConfig_t *config)
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// Deinitialize & Initialize the DMA for new transfer
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// dmaInit must be called before calling HAL_DMA_Init,
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// to enable clock for associated DMA if not already done so.
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dmaInit(dmaIdentifier, OWNER_ADC, RESOURCE_INDEX(dev));
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HAL_DMA_DeInit(&adc->DmaHandle);
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HAL_DMA_Init(&adc->DmaHandle);
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dmaInit(dmaIdentifier, OWNER_ADC, RESOURCE_INDEX(dev));
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// Associate the DMA handle
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__HAL_LINKDMA(&adc->ADCHandle, DMA_Handle, adc->DmaHandle);
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@ -402,11 +402,13 @@ void adcInit(const adcConfig_t *config)
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// Deinitialize & Initialize the DMA for new transfer
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// dmaInit must be called before calling HAL_DMA_Init,
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// to enable clock for associated DMA if not already done so.
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dmaInit(dmaIdentifier, OWNER_ADC, RESOURCE_INDEX(dev));
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HAL_DMA_DeInit(&adc->DmaHandle);
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HAL_DMA_Init(&adc->DmaHandle);
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dmaInit(dmaIdentifier, OWNER_ADC, RESOURCE_INDEX(dev));
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// Associate the DMA handle
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__HAL_LINKDMA(&adc->ADCHandle, DMA_Handle, adc->DmaHandle);
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@ -358,6 +358,8 @@ void i2cInit(I2CDevice device)
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IO_t scl = pDev->scl;
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IO_t sda = pDev->sda;
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RCC_ClockCmd(hardware->rcc, ENABLE);
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IOInit(scl, OWNER_I2C_SCL, RESOURCE_INDEX(device));
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IOInit(sda, OWNER_I2C_SDA, RESOURCE_INDEX(device));
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@ -364,6 +364,18 @@ P - High - High -
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motor->timerDmaIndex = timerDmaIndex(timerHardware->channel);
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}
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dmaIdentifier_e identifier = dmaGetIdentifier(dmaRef);
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#ifdef USE_DSHOT_DMAR
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if (useBurstDshot) {
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dmaInit(identifier, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim));
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dmaSetHandler(identifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, timerIndex);
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} else
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#endif
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{
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dmaInit(identifier, OWNER_MOTOR, RESOURCE_INDEX(motorIndex));
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dmaSetHandler(identifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, motorIndex);
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}
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#ifdef USE_DSHOT_DMAR
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if (useBurstDshot) {
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@ -428,18 +440,6 @@ P - High - High -
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return false;
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}
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dmaIdentifier_e identifier = dmaGetIdentifier(dmaRef);
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#ifdef USE_DSHOT_DMAR
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if (useBurstDshot) {
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dmaInit(identifier, OWNER_TIMUP, timerGetTIMNumber(timerHardware->tim));
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dmaSetHandler(identifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, timerIndex);
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} else
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#endif
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{
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dmaInit(identifier, OWNER_MOTOR, RESOURCE_INDEX(motorIndex));
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dmaSetHandler(identifier, motor_DMA_IRQHandler, NVIC_PRIO_DSHOT_DMA, motorIndex);
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}
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// Start the timer channel now.
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// Enabling/disabling DMA request can restart a new cycle without PWM start/stop.
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@ -25,10 +25,72 @@ void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
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{
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int tag = periphTag >> 5;
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uint32_t mask = 1 << (periphTag & 0x1f);
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#if defined(USE_HAL_DRIVER)
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(void)tag;
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(void)mask;
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(void)NewState;
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#define __HAL_RCC_CLK_ENABLE(bus, enbit) do { \
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__IO uint32_t tmpreg; \
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SET_BIT(RCC->bus ## ENR, enbit); \
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->bus ## ENR, enbit); \
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_CLK_DISABLE(bus, enbit) (RCC->bus ## ENR &= ~(enbit))
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#define __HAL_RCC_CLK(bus, enbit, newState) \
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if (newState == ENABLE) { \
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__HAL_RCC_CLK_ENABLE(bus, enbit); \
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} else { \
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__HAL_RCC_CLK_DISABLE(bus, enbit); \
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}
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switch (tag) {
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case RCC_AHB1:
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__HAL_RCC_CLK(AHB1, mask, NewState);
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break;
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case RCC_AHB2:
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__HAL_RCC_CLK(AHB2, mask, NewState);
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break;
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#ifndef STM32H7
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case RCC_APB1:
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__HAL_RCC_CLK(APB1, mask, NewState);
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break;
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#endif
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case RCC_APB2:
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__HAL_RCC_CLK(APB2, mask, NewState);
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break;
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#ifdef STM32H7
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case RCC_AHB3:
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__HAL_RCC_CLK(AHB3, mask, NewState);
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break;
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case RCC_AHB4:
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__HAL_RCC_CLK(AHB4, mask, NewState);
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break;
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case RCC_APB1L:
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__HAL_RCC_CLK(APB1L, mask, NewState);
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break;
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case RCC_APB1H:
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__HAL_RCC_CLK(APB1H, mask, NewState);
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break;
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case RCC_APB3:
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__HAL_RCC_CLK(APB3, mask, NewState);
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break;
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case RCC_APB4:
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__HAL_RCC_CLK(APB4, mask, NewState);
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break;
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#endif
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}
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#else
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switch (tag) {
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#if defined(STM32F3) || defined(STM32F1)
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@ -55,11 +117,68 @@ void RCC_ResetCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
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{
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int tag = periphTag >> 5;
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uint32_t mask = 1 << (periphTag & 0x1f);
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// Peripheral reset control relies on RSTR bits are identical to ENR bits where applicable
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#define __HAL_RCC_FORCE_RESET(bus, enbit) (RCC->bus ## RSTR |= (enbit))
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#define __HAL_RCC_RELEASE_RESET(bus, enbit) (RCC->bus ## RSTR &= ~(enbit))
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#define __HAL_RCC_RESET(bus, enbit, NewState) \
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if (NewState == ENABLE) { \
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__HAL_RCC_RELEASE_RESET(bus, enbit); \
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} else { \
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__HAL_RCC_FORCE_RESET(bus, enbit); \
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}
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#if defined(USE_HAL_DRIVER)
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(void)tag;
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(void)mask;
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(void)NewState;
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switch (tag) {
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case RCC_AHB1:
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__HAL_RCC_RESET(AHB1, mask, NewState);
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break;
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case RCC_AHB2:
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__HAL_RCC_RESET(AHB2, mask, NewState);
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break;
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#ifndef STM32H7
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case RCC_APB1:
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__HAL_RCC_RESET(APB1, mask, NewState);
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break;
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#endif
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case RCC_APB2:
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__HAL_RCC_RESET(APB2, mask, NewState);
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break;
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#ifdef STM32H7
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case RCC_AHB3:
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__HAL_RCC_RESET(AHB3, mask, NewState);
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break;
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case RCC_AHB4:
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__HAL_RCC_RESET(AHB4, mask, NewState);
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break;
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case RCC_APB1L:
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__HAL_RCC_RESET(APB1L, mask, NewState);
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break;
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case RCC_APB1H:
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__HAL_RCC_RESET(APB1H, mask, NewState);
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break;
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case RCC_APB3:
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__HAL_RCC_RESET(APB3, mask, NewState);
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break;
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case RCC_APB4:
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__HAL_RCC_RESET(APB4, mask, NewState);
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break;
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#endif
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}
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#else
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switch (tag) {
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#if defined(STM32F3) || defined(STM32F10X_CL)
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case RCC_AHB:
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@ -22,10 +22,6 @@
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#include "rcc_types.h"
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// XXX rcc module is not actively used by HAL based platforms (F7 and H7),
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// XXX as peripherals are turned on statically in enableGPIOPowerUsageAndNoiseReductions()
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// XXX during initialization.
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enum rcc_reg {
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RCC_EMPTY = 0, // make sure that default value (0) does not enable anything
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#ifdef STM32H7
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@ -39,7 +35,7 @@ enum rcc_reg {
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RCC_APB3,
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RCC_AHB4,
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RCC_APB4,
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#elif defined(STM32G4)
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#elif defined(STM32G4) || defined(STM32F7)
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RCC_AHB2,
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RCC_APB2,
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RCC_APB1,
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@ -77,5 +73,12 @@ enum rcc_reg {
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#define RCC_AHB2(periph) RCC_ENCODE(RCC_AHB2, RCC_AHB2ENR_ ## periph ## EN)
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#endif
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#ifdef STM32F7
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#define RCC_AHB1(periph) RCC_ENCODE(RCC_AHB1, RCC_AHB1ENR_ ## periph ## EN)
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#define RCC_AHB2(periph) RCC_ENCODE(RCC_AHB2, RCC_AHB2ENR_ ## periph ## EN)
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#define RCC_APB1(periph) RCC_ENCODE(RCC_APB1, RCC_APB1ENR_ ## periph ## EN)
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#define RCC_APB2(periph) RCC_ENCODE(RCC_APB2, RCC_APB2ENR_ ## periph ## EN)
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#endif
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void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState);
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void RCC_ResetCmd(rccPeriphTag_t periphTag, FunctionalState NewState);
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@ -1641,6 +1641,8 @@ bool SD_Init(void)
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{
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SD_Error_t ErrorState;
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__HAL_RCC_SDMMC1_CLK_ENABLE();
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// Initialize SDMMC1 peripheral interface with default configuration for SD card initialization
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MODIFY_REG(SDMMC1->CLKCR, CLKCR_CLEAR_MASK, (uint32_t) SDMMC_INIT_CLK_DIV);
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@ -155,13 +155,7 @@ typedef struct uartHardware_s {
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uartPinDef_t rxPins[UARTHARDWARE_MAX_PINS];
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uartPinDef_t txPins[UARTHARDWARE_MAX_PINS];
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
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uint32_t rcc_ahb1;
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rccPeriphTag_t rcc_apb2;
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rccPeriphTag_t rcc_apb1;
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#else
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rccPeriphTag_t rcc;
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#endif
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#if !defined(STM32F7)
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uint8_t af;
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@ -68,10 +68,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PB14), GPIO_AF4_USART1 }
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#endif
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},
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#ifdef UART1_AHB1_PERIPHERALS
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.rcc_ahb1 = UART1_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART1),
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.rcc = RCC_APB2(USART1),
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1,
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@ -102,10 +99,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PA2), GPIO_AF7_USART2 },
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{ DEFIO_TAG_E(PD5), GPIO_AF7_USART2 }
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},
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#ifdef UART2_AHB1_PERIPHERALS
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.rcc_ahb1 = UART2_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART2),
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.rcc = RCC_APB1(USART2),
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.rxIrq = USART2_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART2,
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@ -138,10 +132,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PC10), GPIO_AF7_USART3 },
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{ DEFIO_TAG_E(PD8), GPIO_AF7_USART3 }
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},
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#ifdef UART3_AHB1_PERIPHERALS
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.rcc_ahb1 = UART3_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(USART3),
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.rcc = RCC_APB1(USART3),
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.rxIrq = USART3_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART3,
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@ -180,10 +171,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PD1), GPIO_AF8_UART4 }
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#endif
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},
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#ifdef UART4_AHB1_PERIPHERALS
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.rcc_ahb1 = UART4_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART4),
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.rcc = RCC_APB1(UART4),
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.rxIrq = UART4_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART4,
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@ -222,10 +210,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PB13), GPIO_AF8_UART5 }
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#endif
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},
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#ifdef UART5_AHB1_PERIPHERALS
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.rcc_ahb1 = UART5_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART5),
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.rcc = RCC_APB1(UART5),
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.rxIrq = UART5_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART5,
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@ -256,10 +241,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PC6), GPIO_AF8_USART6 },
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{ DEFIO_TAG_E(PG14), GPIO_AF8_USART6 }
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},
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#ifdef UART6_AHB1_PERIPHERALS
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.rcc_ahb1 = UART6_AHB1_PERIPHERALS,
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#endif
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.rcc_apb2 = RCC_APB2(USART6),
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.rcc = RCC_APB2(USART6),
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.rxIrq = USART6_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART6,
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@ -298,10 +280,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PB4), GPIO_AF12_UART7 }
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#endif
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},
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#ifdef UART7_AHB1_PERIPHERALS
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.rcc_ahb1 = UART7_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART7),
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.rcc = RCC_APB1(UART7),
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.rxIrq = UART7_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART7_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART7,
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@ -330,10 +309,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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.txPins = {
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{ DEFIO_TAG_E(PE1), GPIO_AF8_UART8 }
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},
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#ifdef UART8_AHB1_PERIPHERALS
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.rcc_ahb1 = UART8_AHB1_PERIPHERALS,
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#endif
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.rcc_apb1 = RCC_APB1(UART8),
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.rcc = RCC_APB1(UART8),
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.rxIrq = UART8_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART8_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART8,
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@ -375,6 +351,10 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode,
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s->Handle.Instance = hardware->reg;
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if (hardware->rcc) {
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RCC_ClockCmd(hardware->rcc, ENABLE);
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}
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IO_t txIO = IOGetByTag(uartdev->tx.pin);
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IO_t rxIO = IOGetByTag(uartdev->rx.pin);
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@ -286,6 +286,10 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode,
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s->Handle.Instance = hardware->reg;
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if (hardware->rcc) {
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RCC_ClockCmd(hardware->rcc, ENABLE);
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}
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IO_t txIO = IOGetByTag(uartdev->tx.pin);
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IO_t rxIO = IOGetByTag(uartdev->rx.pin);
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@ -109,7 +109,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PB6), GPIO_AF4_USART1 },
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{ DEFIO_TAG_E(PB14), GPIO_AF4_USART1 },
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},
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.rcc_apb2 = RCC_APB2(USART1),
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.rcc = RCC_APB2(USART1),
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.rxIrq = USART1_IRQn,
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.txPriority = NVIC_PRIO_SERIALUART1_TXDMA,
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.rxPriority = NVIC_PRIO_SERIALUART1,
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@ -138,7 +138,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
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{ DEFIO_TAG_E(PA2), GPIO_AF7_USART2 },
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{ DEFIO_TAG_E(PD5), GPIO_AF7_USART2 }
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},
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.rcc_apb1 = RCC_APB1L(USART2),
|
||||
.rcc = RCC_APB1L(USART2),
|
||||
.rxIrq = USART2_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART2_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART2,
|
||||
|
@ -169,7 +169,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
{ DEFIO_TAG_E(PC10), GPIO_AF7_USART3 },
|
||||
{ DEFIO_TAG_E(PD8), GPIO_AF7_USART3 }
|
||||
},
|
||||
.rcc_apb1 = RCC_APB1L(USART3),
|
||||
.rcc = RCC_APB1L(USART3),
|
||||
.rxIrq = USART3_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART3_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART3,
|
||||
|
@ -204,7 +204,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
{ DEFIO_TAG_E(PC10), GPIO_AF8_UART4 },
|
||||
{ DEFIO_TAG_E(PD1), GPIO_AF8_UART4 }
|
||||
},
|
||||
.rcc_apb1 = RCC_APB1L(UART4),
|
||||
.rcc = RCC_APB1L(UART4),
|
||||
.rxIrq = UART4_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART4_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART4,
|
||||
|
@ -235,7 +235,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
{ DEFIO_TAG_E(PB13), GPIO_AF14_UART5 },
|
||||
{ DEFIO_TAG_E(PC12), GPIO_AF8_UART5 },
|
||||
},
|
||||
.rcc_apb1 = RCC_APB1L(UART5),
|
||||
.rcc = RCC_APB1L(UART5),
|
||||
.rxIrq = UART5_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART5_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART5,
|
||||
|
@ -264,7 +264,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
{ DEFIO_TAG_E(PC6), GPIO_AF7_USART6 },
|
||||
{ DEFIO_TAG_E(PG14), GPIO_AF7_USART6 }
|
||||
},
|
||||
.rcc_apb2 = RCC_APB2(USART6),
|
||||
.rcc = RCC_APB2(USART6),
|
||||
.rxIrq = USART6_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART6_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART6,
|
||||
|
@ -297,7 +297,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
{ DEFIO_TAG_E(PE8), GPIO_AF7_UART7 },
|
||||
{ DEFIO_TAG_E(PF7), GPIO_AF7_UART7 },
|
||||
},
|
||||
.rcc_apb1 = RCC_APB1L(UART7),
|
||||
.rcc = RCC_APB1L(UART7),
|
||||
.rxIrq = UART7_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART7_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART7,
|
||||
|
@ -324,7 +324,7 @@ const uartHardware_t uartHardware[UARTDEV_COUNT] = {
|
|||
.txPins = {
|
||||
{ DEFIO_TAG_E(PE1), GPIO_AF8_UART8 }
|
||||
},
|
||||
.rcc_apb1 = RCC_APB1L(UART8),
|
||||
.rcc = RCC_APB1L(UART8),
|
||||
.rxIrq = UART8_IRQn,
|
||||
.txPriority = NVIC_PRIO_SERIALUART8_TXDMA,
|
||||
.rxPriority = NVIC_PRIO_SERIALUART8,
|
||||
|
@ -366,6 +366,10 @@ uartPort_t *serialUART(UARTDevice_e device, uint32_t baudRate, portMode_e mode,
|
|||
|
||||
s->Handle.Instance = hardware->reg;
|
||||
|
||||
if (hardware->rcc) {
|
||||
RCC_ClockCmd(hardware->rcc, ENABLE);
|
||||
}
|
||||
|
||||
IO_t txIO = IOGetByTag(uartdev->tx.pin);
|
||||
IO_t rxIO = IOGetByTag(uartdev->rx.pin);
|
||||
|
||||
|
|
|
@ -61,82 +61,6 @@ void systemResetToBootloader(bootloaderRequestType_e requestType)
|
|||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
void enableGPIOPowerUsageAndNoiseReductions(void)
|
||||
{
|
||||
|
||||
// AHB1
|
||||
__HAL_RCC_BKPSRAM_CLK_ENABLE();
|
||||
__HAL_RCC_DTCMRAMEN_CLK_ENABLE();
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
|
||||
__HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
#ifndef STM32F722xx
|
||||
__HAL_RCC_DMA2D_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOK_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
//APB1
|
||||
__HAL_RCC_TIM2_CLK_ENABLE();
|
||||
__HAL_RCC_TIM3_CLK_ENABLE();
|
||||
__HAL_RCC_TIM4_CLK_ENABLE();
|
||||
__HAL_RCC_TIM5_CLK_ENABLE();
|
||||
__HAL_RCC_TIM6_CLK_ENABLE();
|
||||
__HAL_RCC_TIM7_CLK_ENABLE();
|
||||
__HAL_RCC_TIM12_CLK_ENABLE();
|
||||
__HAL_RCC_TIM13_CLK_ENABLE();
|
||||
__HAL_RCC_TIM14_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI2_CLK_ENABLE();
|
||||
__HAL_RCC_SPI3_CLK_ENABLE();
|
||||
__HAL_RCC_USART2_CLK_ENABLE();
|
||||
__HAL_RCC_USART3_CLK_ENABLE();
|
||||
__HAL_RCC_UART4_CLK_ENABLE();
|
||||
__HAL_RCC_UART5_CLK_ENABLE();
|
||||
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
__HAL_RCC_I2C3_CLK_ENABLE();
|
||||
__HAL_RCC_CAN1_CLK_ENABLE();
|
||||
__HAL_RCC_DAC_CLK_ENABLE();
|
||||
__HAL_RCC_UART7_CLK_ENABLE();
|
||||
__HAL_RCC_UART8_CLK_ENABLE();
|
||||
#ifndef STM32F722xx
|
||||
__HAL_RCC_I2C4_CLK_ENABLE();
|
||||
__HAL_RCC_CAN2_CLK_ENABLE();
|
||||
__HAL_RCC_CEC_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
//APB2
|
||||
__HAL_RCC_TIM1_CLK_ENABLE();
|
||||
__HAL_RCC_TIM8_CLK_ENABLE();
|
||||
__HAL_RCC_USART1_CLK_ENABLE();
|
||||
__HAL_RCC_USART6_CLK_ENABLE();
|
||||
__HAL_RCC_ADC1_CLK_ENABLE();
|
||||
__HAL_RCC_ADC2_CLK_ENABLE();
|
||||
__HAL_RCC_ADC3_CLK_ENABLE();
|
||||
__HAL_RCC_SDMMC1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI4_CLK_ENABLE();
|
||||
__HAL_RCC_TIM9_CLK_ENABLE();
|
||||
__HAL_RCC_TIM10_CLK_ENABLE();
|
||||
__HAL_RCC_TIM11_CLK_ENABLE();
|
||||
__HAL_RCC_SPI5_CLK_ENABLE();
|
||||
__HAL_RCC_SAI1_CLK_ENABLE();
|
||||
__HAL_RCC_SAI2_CLK_ENABLE();
|
||||
#ifndef STM32F722xx
|
||||
__HAL_RCC_SPI6_CLK_ENABLE();
|
||||
#endif
|
||||
}
|
||||
|
||||
bool isMPUSoftReset(void)
|
||||
{
|
||||
if (cachedRccCsrValue & RCC_CSR_SFTRSTF)
|
||||
|
@ -187,8 +111,6 @@ void systemInit(void)
|
|||
|
||||
//RCC_ClearFlag();
|
||||
|
||||
enableGPIOPowerUsageAndNoiseReductions();
|
||||
|
||||
// Init cycle counter
|
||||
cycleCounterInit();
|
||||
|
||||
|
|
|
@ -31,95 +31,6 @@
|
|||
|
||||
void SystemClock_Config(void);
|
||||
|
||||
|
||||
void enablePeripherialClocks(void)
|
||||
{
|
||||
__HAL_RCC_MDMA_CLK_ENABLE();
|
||||
__HAL_RCC_QSPI_CLK_ENABLE();
|
||||
|
||||
// AHB1
|
||||
__HAL_RCC_DMA1_CLK_ENABLE();
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
__HAL_RCC_ADC12_CLK_ENABLE();
|
||||
// USB clock will be enabled by vcpXXX/usbd_conf.c
|
||||
// Note that enabling both ULPI and non-ULPI does not work.
|
||||
|
||||
// AHB2
|
||||
__HAL_RCC_D2SRAM1_CLK_ENABLE();
|
||||
__HAL_RCC_D2SRAM2_CLK_ENABLE();
|
||||
__HAL_RCC_D2SRAM3_CLK_ENABLE();
|
||||
|
||||
// AHB4
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOK_CLK_ENABLE();
|
||||
__HAL_RCC_BDMA_CLK_ENABLE();
|
||||
__HAL_RCC_ADC3_CLK_ENABLE();
|
||||
|
||||
// APB3
|
||||
|
||||
// APB1
|
||||
__HAL_RCC_TIM2_CLK_ENABLE();
|
||||
__HAL_RCC_TIM3_CLK_ENABLE();
|
||||
__HAL_RCC_TIM4_CLK_ENABLE();
|
||||
__HAL_RCC_TIM5_CLK_ENABLE();
|
||||
__HAL_RCC_TIM6_CLK_ENABLE();
|
||||
__HAL_RCC_TIM7_CLK_ENABLE();
|
||||
__HAL_RCC_TIM12_CLK_ENABLE();
|
||||
__HAL_RCC_TIM13_CLK_ENABLE();
|
||||
__HAL_RCC_TIM14_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI2_CLK_ENABLE();
|
||||
__HAL_RCC_SPI3_CLK_ENABLE();
|
||||
__HAL_RCC_USART2_CLK_ENABLE();
|
||||
__HAL_RCC_USART3_CLK_ENABLE();
|
||||
__HAL_RCC_UART4_CLK_ENABLE();
|
||||
__HAL_RCC_UART5_CLK_ENABLE();
|
||||
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
__HAL_RCC_I2C3_CLK_ENABLE();
|
||||
__HAL_RCC_DAC12_CLK_ENABLE();
|
||||
__HAL_RCC_UART7_CLK_ENABLE();
|
||||
__HAL_RCC_UART8_CLK_ENABLE();
|
||||
__HAL_RCC_CRS_CLK_ENABLE();
|
||||
|
||||
// APB2
|
||||
__HAL_RCC_TIM1_CLK_ENABLE();
|
||||
__HAL_RCC_TIM8_CLK_ENABLE();
|
||||
__HAL_RCC_USART1_CLK_ENABLE();
|
||||
__HAL_RCC_USART6_CLK_ENABLE();
|
||||
__HAL_RCC_SPI1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI4_CLK_ENABLE();
|
||||
__HAL_RCC_TIM15_CLK_ENABLE();
|
||||
__HAL_RCC_TIM16_CLK_ENABLE();
|
||||
__HAL_RCC_TIM17_CLK_ENABLE();
|
||||
__HAL_RCC_SPI5_CLK_ENABLE();
|
||||
|
||||
// APB4
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
__HAL_RCC_LPUART1_CLK_ENABLE();
|
||||
__HAL_RCC_SPI6_CLK_ENABLE();
|
||||
__HAL_RCC_I2C4_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM2_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM3_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM4_CLK_ENABLE();
|
||||
__HAL_RCC_LPTIM5_CLK_ENABLE();
|
||||
__HAL_RCC_COMP12_CLK_ENABLE();
|
||||
__HAL_RCC_VREF_CLK_ENABLE();
|
||||
}
|
||||
|
||||
void enableGPIOPowerUsageAndNoiseReductions(void)
|
||||
{
|
||||
}
|
||||
|
||||
void configureMasterClockOutputs(void)
|
||||
{
|
||||
// Initialize pins for MCO1 and MCO2 for clock testing/verification
|
||||
|
@ -166,9 +77,9 @@ void systemInit(void)
|
|||
|
||||
//RCC_ClearFlag();
|
||||
|
||||
enablePeripherialClocks();
|
||||
|
||||
enableGPIOPowerUsageAndNoiseReductions();
|
||||
__HAL_RCC_D2SRAM1_CLK_ENABLE();
|
||||
__HAL_RCC_D2SRAM2_CLK_ENABLE();
|
||||
__HAL_RCC_D2SRAM3_CLK_ENABLE();
|
||||
|
||||
#ifdef USE_MCO_OUTPUTS
|
||||
configureMasterClockOutputs();
|
||||
|
|
Loading…
Reference in New Issue