Support the Sparky board by peabody124 - work in progress, not flight
ready. https://github.com/TauLabs/TauLabs/wiki/Sparky http://buildandcrash.blogspot.co.uk/2013/05/sparky-testing-and-building-no-crashing.html
This commit is contained in:
Dominic Clifton
parent
fed6df275f
commit
6c96b8dd86
10
Makefile
10
Makefile
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@ -35,7 +35,7 @@ SERIAL_DEVICE ?= /dev/ttyUSB0
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FORKNAME = cleanflight
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VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 CC3D CJMCU EUSTM32F103RC MASSIVEF3 PORT103R
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VALID_TARGETS = NAZE NAZE32PRO OLIMEXINO STM32F3DISCOVERY CHEBUZZF3 CC3D CJMCU EUSTM32F103RC MASSIVEF3 PORT103R SPARKY
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# Valid targets for OP BootLoader support
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OPBL_VALID_TARGETS = CC3D
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@ -54,7 +54,7 @@ LINKER_DIR = $(ROOT)/src/main/target
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# Search path for sources
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VPATH := $(SRC_DIR):$(SRC_DIR)/startup
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ifeq ($(TARGET),$(filter $(TARGET),STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO MASSIVEF3))
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ifeq ($(TARGET),$(filter $(TARGET),STM32F3DISCOVERY CHEBUZZF3 NAZE32PRO MASSIVEF3 SPARKY))
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STDPERIPH_DIR = $(ROOT)/lib/main/STM32F30x_StdPeriph_Driver
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USBFS_DIR = $(ROOT)/lib/main/STM32_USB-FS-Device_Driver
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@ -423,6 +423,12 @@ MASSIVEF3_SRC = $(STM32F3DISCOVERY_SRC) \
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$(HIGHEND_SRC) \
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$(COMMON_SRC)
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SPARKY_SRC = $(STM32F30x_COMMON_SRC) \
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drivers/accgyro_mpu9150.c \
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drivers/barometer_ms5611.c \
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$(HIGHEND_SRC) \
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$(COMMON_SRC)
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ifeq ($(TARGET),MASSIVEF3)
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LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f303_128k.ld
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endif
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@ -230,6 +230,41 @@ static const uint16_t airPPM[] = {
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0xFFFF
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};
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static const uint16_t airPWM[] = {
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0xFFFF
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};
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#endif
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#ifdef SPARKY
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static const uint16_t multiPPM[] = {
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#if 1
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0xFFFF
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#else
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PWM13 | (MAP_TO_PPM_INPUT << 8), // PPM input
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PWM1 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM3 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM4 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM5 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM6 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM7 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM9 | (MAP_TO_MOTOR_OUTPUT << 8),
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PWM8 | (MAP_TO_SERVO_OUTPUT << 8),
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PWM10 | (MAP_TO_SERVO_OUTPUT << 8),
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PWM11 | (MAP_TO_SERVO_OUTPUT << 8),
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PWM12 | (MAP_TO_SERVO_OUTPUT << 8),
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0xFFFF
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#endif
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};
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static const uint16_t multiPWM[] = {
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0xFFFF
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};
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static const uint16_t airPPM[] = {
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0xFFFF
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};
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static const uint16_t airPWM[] = {
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0xFFFF
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};
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@ -334,7 +369,7 @@ pwmOutputConfiguration_t *pwmInit(drv_pwm_config_t *init)
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type = MAP_TO_SERVO_OUTPUT;
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#endif
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#if (defined(STM32F303xC) || defined(STM32F3DISCOVERY)) && !defined(CHEBUZZF3)
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#if defined(NAZE32PRO) || (defined(STM32F3DISCOVERY) && !defined(CHEBUZZF3))
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// remap PWM 5+6 or 9+10 as servos - softserial pin pairs require timer ports that use the same timer
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if (init->useSoftSerial) {
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if (timerIndex == PWM5 || timerIndex == PWM6)
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@ -175,6 +175,47 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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#endif
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#ifdef SPARKY
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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//
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// 6 x 3 pin headers
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//
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{ TIM1, GPIOB, Pin_15, TIM_Channel_3, TIM1_CC_IRQn, 0, Mode_AF_PP, GPIO_PinSource15, GPIO_AF_4}, // PWM1 - PB15 - TIM1_CH3N, TIM15_CH1N, !TIM15_CH2
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{ TIM1, GPIOB, Pin_14, TIM_Channel_2, TIM1_CC_IRQn, 0, Mode_AF_PP, GPIO_PinSource14, GPIO_AF_6}, // PWM2 - PB14 - TIM1_CH2N, TIM15_CH1
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{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 0, Mode_AF_PP, GPIO_PinSource8, GPIO_AF_6}, // PWM3 - PA8 - TIM1_CH1, TIM4_ETR
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{ TIM3, GPIOB, Pin_0, TIM_Channel_3, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_2}, // PWM4 - PB0 - *TIM3_CH3, TIM1_CH2N, TIM8_CH2N
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{ TIM3, GPIOA, Pin_6, TIM_Channel_1, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource6, GPIO_AF_2}, // PWM5 - PA6 - *TIM3_CH1, TIM8_BKIN, TIM1_BKIN, TIM16_CH1
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{ TIM15, GPIOA, Pin_2, TIM_Channel_1, TIM1_BRK_TIM15_IRQn, 0, Mode_AF_PP, GPIO_PinSource2, GPIO_AF_9}, // PWM6 - PA2 - !TIM2_CH3, *TIM15_CH1
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//
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// 6 pin header
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//
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// PWM7-10
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{ TIM3, GPIOB, Pin_1, TIM_Channel_4, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_2}, // PWM7 - PB1 - *TIM3_CH4, TIM1_CH3N, TIM8_CH3N
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{ TIM17, GPIOA, Pin_7, TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, 0, Mode_AF_PP, GPIO_PinSource7, GPIO_AF_1}, // PWM8 - PA7 - !TIM3_CH2, *TIM17_CH1, TIM1_CH1N, TIM8_CH1
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{ TIM3, GPIOA, Pin_4, TIM_Channel_2, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource4, GPIO_AF_2}, // PWM9 - PA4 - *TIM3_CH2
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{ TIM2, GPIOA, Pin_1, TIM_Channel_2, TIM2_IRQn, 0, Mode_AF_PP, GPIO_PinSource1, GPIO_AF_1}, // PWM10 - PA1 - *TIM2_CH2, TIM15_CH1N
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// USART3 RX/TX
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{ TIM2, GPIOB, Pin_11, TIM_Channel_4, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_1}, // RX - PB11 - *TIM2_CH4, USART3_RX (AF7) - PWM11
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{ TIM2, GPIOB, Pin_10, TIM_Channel_3, TIM3_IRQn, 0, Mode_AF_PP, GPIO_PinSource0, GPIO_AF_1}, // TX - PB10 - *TIM2_CH3, USART3_TX (AF7) - PWM12
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//
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// PPM PORT - Also USART2 RX (AF5)
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//
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{ TIM15, GPIOA, Pin_3, TIM_Channel_2, TIM1_BRK_TIM15_IRQn, 0, Mode_AF_PP, GPIO_PinSource15, GPIO_AF_9}, // PPM - PA3 - !TIM2_CH4, *TIM15_CH2 - PWM13
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};
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#define USED_TIMERS (TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(15) | TIM_N(17))
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#define TIMER_APB1_PERIPHERALS (RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3)
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#define TIMER_APB2_PERIPHERALS (RCC_APB2Periph_TIM1 | RCC_APB2Periph_TIM15 | RCC_APB2Periph_TIM17)
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#define TIMER_AHB_PERIPHERALS (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB)
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#endif
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#define USED_TIMER_COUNT BITCOUNT(USED_TIMERS)
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#define CC_CHANNELS_PER_TIMER 4 // TIM_Channel_1..4
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@ -17,6 +17,10 @@
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#pragma once
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#ifdef SPARKY
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#define USABLE_TIMER_CHANNEL_COUNT 13
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#endif
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#ifdef CHEBUZZF3
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#define USABLE_TIMER_CHANNEL_COUNT 18
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#endif
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@ -200,6 +200,7 @@ void init(void)
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#endif
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#endif
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#if !defined(SPARKY)
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adc_params.enableRSSI = feature(FEATURE_RSSI_ADC);
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adc_params.enableCurrentMeter = feature(FEATURE_CURRENT_METER);
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adc_params.enableExternal1 = false;
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@ -212,6 +213,8 @@ void init(void)
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#endif
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adcInit(&adc_params);
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#endif
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initBoardAlignment(&masterConfig.boardAlignment);
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@ -0,0 +1,372 @@
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/**
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******************************************************************************
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* @file system_stm32f30x.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 28-March-2014
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F30x devices,
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* and is generated by the clock configuration tool
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* stm32f30x_Clock_Configuration_V1.0.0.xls
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f30x.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (8 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and HSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
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* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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* Supported STM32F30x device
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 72000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 72000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 12000000
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*----------------------------------------------------------------------------
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* PLLMUL | 6
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*-----------------------------------------------------------------------------
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* PREDIV | 1
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*-----------------------------------------------------------------------------
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* USB Clock | ENABLE
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 2
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f30x_system
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* @{
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*/
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/** @addtogroup STM32F30x_System_Private_Includes
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* @{
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*/
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#include "stm32f30x.h"
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uint32_t hse_value = HSE_VALUE;
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/**
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* @}
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*/
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/* Private typedef -----------------------------------------------------------*/
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/** @addtogroup STM32F30x_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @addtogroup STM32F30x_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 72000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
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* @{
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*/
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void SetSysClock(void);
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR &= 0xF87FC00C;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/* Reset PREDIV1[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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/* Reset USARTSW[1:0], I2CSW and TIMs bits */
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RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings ----------------------------------*/
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//SetSysClock(); // called from main()
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
|
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* be used by the user application to setup the SysTick timer or configure
|
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* other parameters.
|
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*
|
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* @note Each time the core clock (HCLK) changes, this function must be called
|
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
|
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* 8 MHz) but the real value may vary depending on the variations
|
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
|
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
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* frequency of the crystal used. Otherwise, this function may
|
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* have wrong result.
|
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*
|
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* - The result of this function could be not correct when using fractional
|
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* value for HSE crystal.
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*
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* @param None
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* @retval None
|
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock */
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||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK / 2 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 28-March-2014
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F30X_H
|
||||
#define __SYSTEM_STM32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F30X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* This file is part of Cleanflight.
|
||||
*
|
||||
* Cleanflight is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* Cleanflight is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define TARGET_BOARD_IDENTIFIER "SPKY" // SParKY
|
||||
|
||||
#define LED0_GPIO GPIOB
|
||||
#define LED0_PIN Pin_4 // Blue LEDs - PB4
|
||||
#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOB
|
||||
#define LED1_GPIO GPIOB
|
||||
#define LED1_PIN Pin_5 // Green LEDs - PB5
|
||||
#define LED1_PERIPHERAL RCC_AHBPeriph_GPIOB
|
||||
|
||||
// MPU 9150 INT connected to PA15, pulled up to VCC by 10K Resistor
|
||||
#define GYRO
|
||||
#define USE_GYRO_MPU9150
|
||||
|
||||
#define ACC
|
||||
#define USE_ACC_MPU9150
|
||||
|
||||
#define BARO
|
||||
#define USE_BARO_MS5611
|
||||
|
||||
#define LED0
|
||||
#define LED1
|
||||
|
||||
#define USE_VCP
|
||||
#define USE_USART1 // Conn 1 - TX (PB6) RX PB7
|
||||
#define USE_USART2 // Input - RX (PA3)
|
||||
#define USE_USART3 // Servo out - 10/RX (PB11) 11/TX (PB10)
|
||||
#define SERIAL_PORT_COUNT 4
|
||||
|
||||
// Note: PA5 and PA0 are N/C on the sparky - potentially use for ADC or LED STRIP?
|
||||
|
||||
#define USE_I2C
|
||||
#define I2C_DEVICE (I2CDEV_2) // SDA (PA10/AF4), SCL (PA9/AF4)
|
||||
|
||||
#define I2C2_SCL_GPIO GPIOA
|
||||
#define I2C2_SCL_GPIO_AF GPIO_AF_4
|
||||
#define I2C2_SCL_PIN GPIO_Pin_9
|
||||
#define I2C2_SCL_PIN_SOURCE GPIO_PinSource9
|
||||
#define I2C2_SCL_CLK_SOURCE RCC_AHBPeriph_GPIOA
|
||||
#define I2C2_SDA_GPIO GPIOA
|
||||
#define I2C2_SDA_GPIO_AF GPIO_AF_4
|
||||
#define I2C2_SDA_PIN GPIO_Pin_10
|
||||
#define I2C2_SDA_PIN_SOURCE GPIO_PinSource10
|
||||
#define I2C2_SDA_CLK_SOURCE RCC_AHBPeriph_GPIOA
|
||||
|
||||
|
||||
#define SENSORS_SET (SENSOR_ACC)
|
||||
|
||||
Loading…
Reference in New Issue