commit
750fb11d09
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@ -64,16 +64,22 @@ static uint8_t allocatedOutputPortCount = 0;
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static bool pwmMotorsEnabled = true;
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static void pwmOCConfig(TIM_TypeDef *tim, uint8_t channel, uint16_t value, uint8_t ouputPolarity)
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static void pwmOCConfig(TIM_TypeDef *tim, uint8_t channel, uint16_t value, uint8_t output)
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{
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TIM_OCInitTypeDef TIM_OCInitStructure;
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TIM_OCStructInit(&TIM_OCInitStructure);
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TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
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TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
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TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
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if (output & TIMER_OUTPUT_N_CHANNEL) {
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TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable;
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TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
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}
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else {
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TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
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TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
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}
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TIM_OCInitStructure.TIM_Pulse = value;
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TIM_OCInitStructure.TIM_OCPolarity = ouputPolarity ? TIM_OCPolarity_High : TIM_OCPolarity_Low;
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TIM_OCInitStructure.TIM_OCPolarity = (output & TIMER_OUTPUT_INVERTED) ? TIM_OCPolarity_High : TIM_OCPolarity_Low;
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TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
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switch (channel) {
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@ -106,7 +112,7 @@ static pwmOutputPort_t *pwmOutConfig(const timerHardware_t *timerHardware, uint8
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IOInit(io, OWNER_MOTOR, RESOURCE_OUTPUT, allocatedOutputPortCount);
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IOConfigGPIO(io, IOCFG_AF_PP);
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pwmOCConfig(timerHardware->tim, timerHardware->channel, value, timerHardware->output & TIMER_OUTPUT_INVERTED);
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pwmOCConfig(timerHardware->tim, timerHardware->channel, value, timerHardware->output);
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if (timerHardware->output & TIMER_OUTPUT_ENABLED) {
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TIM_CtrlPWMOutputs(timerHardware->tim, ENABLE);
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@ -88,7 +88,8 @@ typedef struct timerHardware_s {
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enum {
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TIMER_OUTPUT_ENABLED = 0x01,
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TIMER_OUTPUT_INVERTED = 0x02
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TIMER_OUTPUT_INVERTED = 0x02,
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TIMER_OUTPUT_N_CHANNEL= 0x04
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};
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#ifdef STM32F1
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@ -65,8 +65,10 @@ const uint16_t airPWM[] = {
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const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
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{ TIM1, IO_TAG(PA8), TIM_Channel_1, TIM1_CC_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_6},
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{ TIM3, IO_TAG(PB0), TIM_Channel_3, TIM3_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_2},
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{ TIM15, IO_TAG(PB14), TIM_Channel_1, TIM1_BRK_TIM15_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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{ TIM15, IO_TAG(PB15), TIM_Channel_2, TIM1_BRK_TIM15_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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{ TIM1, IO_TAG(PB14), TIM_Channel_2, TIM1_CC_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_N_CHANNEL, IOCFG_AF_PP, GPIO_AF_6}, // TIM1_CH2N
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{ TIM1, IO_TAG(PB15), TIM_Channel_3, TIM1_CC_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_N_CHANNEL, IOCFG_AF_PP, GPIO_AF_4}, // TIM1_CH3N
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//{ TIM15, IO_TAG(PB14), TIM_Channel_1, TIM1_BRK_TIM15_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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//{ TIM15, IO_TAG(PB15), TIM_Channel_2, TIM1_BRK_TIM15_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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{ TIM16, IO_TAG(PA6), TIM_Channel_1, TIM1_UP_TIM16_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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{ TIM17, IO_TAG(PA7), TIM_Channel_1, TIM1_TRG_COM_TIM17_IRQn, TIMER_OUTPUT_ENABLED|TIMER_OUTPUT_INVERTED, IOCFG_AF_PP, GPIO_AF_1},
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