Fix clock initialisation on new revision CJMCU boards.

lib/main/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c

@@ -141,7 +141,12 @@ void SetSysClock(bool overclock)
     *RCC_CRH |= (uint32_t)0x8 << (RCC_CFGR_PLLMULL9 >> 16);
     GPIOC->ODR &= (uint32_t)~(CAN_MCR_RESET);
 	
+#if defined(CJMCU)
+    // On CJMCU new revision boards (Late 2014) bit 15 of GPIOC->IDR is '1'.
+    RCC_CFGR_PLLMUL = RCC_CFGR_PLLMULL9;
+#else
     RCC_CFGR_PLLMUL = GPIOC->IDR & CAN_MCR_RESET ? hse_value = 12000000, RCC_CFGR_PLLMULL6 : RCC_CFGR_PLLMULL9;
+#endif
     switch (clocksrc) {
         case SRC_HSE:
             if (overclock) {