diff --git a/src/main/drivers/timer_def.h b/src/main/drivers/timer_def.h index d32716b1a..f27f79692 100644 --- a/src/main/drivers/timer_def.h +++ b/src/main/drivers/timer_def.h @@ -297,9 +297,8 @@ #define DEF_TIM_DMA_STR_0__TIM3_CH4 DMA1_ST2 #define DEF_TIM_DMA_STR_0__TIM4_CH1 DMA1_ST0 -#define DEF_TIM_DMA_STR_0__TIM4_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM4_CH2 DMA1_ST3 #define DEF_TIM_DMA_STR_0__TIM4_CH3 DMA1_ST7 -#define DEF_TIM_DMA_STR_0__TIM4_CH4 DMA1_ST3 #define DEF_TIM_DMA_STR_0__TIM5_CH1 DMA1_ST2 #define DEF_TIM_DMA_STR_0__TIM5_CH2 DMA1_ST4 @@ -321,6 +320,8 @@ #define DEF_TIM_DMA_STR_1__TIM8_CH3N DMA2_ST4 #define DEF_TIM_DMA_STR_0__TIM8_CH4 DMA2_ST7 +#define DEF_TIM_DMA_STR_0__TIM4_CH4 DMA_NONE + #define DEF_TIM_DMA_STR_0__TIM9_CH1 DMA_NONE #define DEF_TIM_DMA_STR_0__TIM9_CH2 DMA_NONE @@ -367,7 +368,6 @@ #define DEF_TIM_DMA_CHN_0__TIM4_CH1 DMA_Channel_2 #define DEF_TIM_DMA_CHN_0__TIM4_CH2 DMA_Channel_2 #define DEF_TIM_DMA_CHN_0__TIM4_CH3 DMA_Channel_2 -#define DEF_TIM_DMA_CHN_0__TIM4_CH4 DMA_Channel_2 #define DEF_TIM_DMA_CHN_0__TIM5_CH1 DMA_Channel_6 #define DEF_TIM_DMA_CHN_0__TIM5_CH2 DMA_Channel_6 @@ -389,6 +389,8 @@ #define DEF_TIM_DMA_CHN_1__TIM8_CH3N DMA_Channel_7 #define DEF_TIM_DMA_CHN_0__TIM8_CH4 DMA_Channel_7 +#define DEF_TIM_DMA_CHN_0__TIM4_CH4 0 + #define DEF_TIM_DMA_CHN_0__TIM9_CH1 0 #define DEF_TIM_DMA_CHN_0__TIM9_CH2 0 @@ -420,6 +422,290 @@ #define DMA2_ST6_STREAM DMA2_Stream6 #define DMA2_ST7_STREAM DMA2_Stream7 +#elif defined(STM32F7) +#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) {\ + tim,\ + IO_TAG(pin),\ + EXPAND(DEF_CHAN_ ## chan),\ + flags,\ + (DEF_CHAN_ ## chan ## _OUTPUT | out),\ + EXPAND(GPIO_AF__ ## pin ## _ ## tim ## _ ## chan),\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM),\ + EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan),\ + CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER)\ + } + +#define DEF_DMA_CHANNEL(tim, chan, dmaopt) EXPAND(DEF_TIM_DMA_CHN_ ## dmaopt ## __ ## tim ## _ ## chan) +#define DEF_DMA_STREAM(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _STREAM) +#define DEF_DMA_HANDLER(tim, chan, dmaopt) CONCAT(EXPAND(DEF_TIM_DMA_STR_ ## dmaopt ## __ ## tim ## _ ## chan), _HANDLER) + +/* F7 Stream Mappings */ + +#define DEF_TIM_DMA_STR_0__TIM1_CH1 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH1 DMA2_ST1 +#define DEF_TIM_DMA_STR_2__TIM1_CH1 DMA2_ST3 +#define DEF_TIM_DMA_STR_0__TIM1_CH1N DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH1N DMA2_ST1 +#define DEF_TIM_DMA_STR_2__TIM1_CH1N DMA2_ST3 +#define DEF_TIM_DMA_STR_0__TIM1_CH2 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM1_CH2N DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH2N DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH3 DMA2_ST6 +#define DEF_TIM_DMA_STR_0__TIM1_CH3N DMA2_ST6 +#define DEF_TIM_DMA_STR_1__TIM1_CH3N DMA2_ST6 +#define DEF_TIM_DMA_STR_0__TIM1_CH4 DMA2_ST4 + +#define DEF_TIM_DMA_STR_0__TIM2_CH1 DMA1_ST5 +#define DEF_TIM_DMA_STR_0__TIM2_CH2 DMA1_ST6 +#define DEF_TIM_DMA_STR_0__TIM2_CH3 DMA1_ST1 +#define DEF_TIM_DMA_STR_0__TIM2_CH4 DMA1_ST7 +#define DEF_TIM_DMA_STR_1__TIM2_CH4 DMA1_ST6 + +#define DEF_TIM_DMA_STR_0__TIM3_CH1 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM3_CH2 DMA1_ST5 +#define DEF_TIM_DMA_STR_0__TIM3_CH3 DMA1_ST7 +#define DEF_TIM_DMA_STR_0__TIM3_CH4 DMA1_ST2 + +#define DEF_TIM_DMA_STR_0__TIM4_CH1 DMA1_ST0 +#define DEF_TIM_DMA_STR_0__TIM4_CH2 DMA1_ST3 +#define DEF_TIM_DMA_STR_0__TIM4_CH3 DMA1_ST7 + +#define DEF_TIM_DMA_STR_0__TIM5_CH1 DMA1_ST2 +#define DEF_TIM_DMA_STR_0__TIM5_CH2 DMA1_ST4 +#define DEF_TIM_DMA_STR_0__TIM5_CH3 DMA1_ST0 +#define DEF_TIM_DMA_STR_0__TIM5_CH4 DMA1_ST1 +#define DEF_TIM_DMA_STR_1__TIM5_CH4 DMA1_ST3 + +#define DEF_TIM_DMA_STR_0__TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_1__TIM8_CH1 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH1N DMA2_ST2 +#define DEF_TIM_DMA_STR_1__TIM8_CH1N DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH2 DMA2_ST3 +#define DEF_TIM_DMA_STR_1__TIM8_CH2 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH2N DMA2_ST3 +#define DEF_TIM_DMA_STR_1__TIM8_CH2N DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH3 DMA2_ST4 +#define DEF_TIM_DMA_STR_1__TIM8_CH3 DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH3N DMA2_ST4 +#define DEF_TIM_DMA_STR_1__TIM8_CH3N DMA2_ST2 +#define DEF_TIM_DMA_STR_0__TIM8_CH4 DMA2_ST7 + +#define DEF_TIM_DMA_STR_0__TIM4_CH4 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM9_CH1 DMA_NONE +#define DEF_TIM_DMA_STR_0__TIM9_CH2 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM10_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM11_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM12_CH1 DMA_NONE +#define DEF_TIM_DMA_STR_0__TIM12_CH2 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM13_CH1 DMA_NONE + +#define DEF_TIM_DMA_STR_0__TIM14_CH1 DMA_NONE + +/* F7 Channel Mappings */ + +#define DEF_TIM_DMA_CHN_0__TIM1_CH1 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH1 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_2__TIM1_CH1 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH1N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH1N DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_2__TIM1_CH1N DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH2 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH2 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH2N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH2N DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH3 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH3 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH3N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_1__TIM1_CH3N DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM1_CH4 DMA_CHANNEL_6 + +#define DEF_TIM_DMA_CHN_0__TIM2_CH1 DMA_CHANNEL_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH2 DMA_CHANNEL_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH3 DMA_CHANNEL_3 +#define DEF_TIM_DMA_CHN_0__TIM2_CH4 DMA_CHANNEL_3 +#define DEF_TIM_DMA_CHN_1__TIM2_CH4 DMA_CHANNEL_3 + +#define DEF_TIM_DMA_CHN_0__TIM3_CH1 DMA_CHANNEL_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH2 DMA_CHANNEL_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH3 DMA_CHANNEL_5 +#define DEF_TIM_DMA_CHN_0__TIM3_CH4 DMA_CHANNEL_5 + +#define DEF_TIM_DMA_CHN_0__TIM4_CH1 DMA_CHANNEL_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH2 DMA_CHANNEL_2 +#define DEF_TIM_DMA_CHN_0__TIM4_CH3 DMA_CHANNEL_2 + +#define DEF_TIM_DMA_CHN_0__TIM5_CH1 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM5_CH2 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM5_CH3 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_0__TIM5_CH4 DMA_CHANNEL_6 +#define DEF_TIM_DMA_CHN_1__TIM5_CH4 DMA_CHANNEL_6 + +#define DEF_TIM_DMA_CHN_0__TIM8_CH1 DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH1 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH1N DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH1N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH2 DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH2 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH2N DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH2N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH3 DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH3 DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH3N DMA_CHANNEL_7 +#define DEF_TIM_DMA_CHN_1__TIM8_CH3N DMA_CHANNEL_0 +#define DEF_TIM_DMA_CHN_0__TIM8_CH4 DMA_CHANNEL_7 + +#define DEF_TIM_DMA_CHN_0__TIM4_CH4 0 + +#define DEF_TIM_DMA_CHN_0__TIM9_CH1 0 +#define DEF_TIM_DMA_CHN_0__TIM9_CH2 0 + +#define DEF_TIM_DMA_CHN_0__TIM10_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM11_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM12_CH1 0 +#define DEF_TIM_DMA_CHN_0__TIM12_CH2 0 + +#define DEF_TIM_DMA_CHN_0__TIM13_CH1 0 + +#define DEF_TIM_DMA_CHN_0__TIM14_CH1 0 + +#define DMA1_ST0_STREAM DMA1_Stream0 +#define DMA1_ST1_STREAM DMA1_Stream1 +#define DMA1_ST2_STREAM DMA1_Stream2 +#define DMA1_ST3_STREAM DMA1_Stream3 +#define DMA1_ST4_STREAM DMA1_Stream4 +#define DMA1_ST5_STREAM DMA1_Stream5 +#define DMA1_ST6_STREAM DMA1_Stream6 +#define DMA1_ST7_STREAM DMA1_Stream7 +#define DMA2_ST0_STREAM DMA2_Stream0 +#define DMA2_ST1_STREAM DMA2_Stream1 +#define DMA2_ST2_STREAM DMA2_Stream2 +#define DMA2_ST3_STREAM DMA2_Stream3 +#define DMA2_ST4_STREAM DMA2_Stream4 +#define DMA2_ST5_STREAM DMA2_Stream5 +#define DMA2_ST6_STREAM DMA2_Stream6 +#define DMA2_ST7_STREAM DMA2_Stream7 + +#define GPIO_AF(p, t) CONCAT(GPIO_AF__, p, _, t) + +//PORTA +#define GPIO_AF__PA0_TIM2_CH1 GPIO_AF1_TIM2 +#define GPIO_AF__PA1_TIM2_CH2 GPIO_AF1_TIM2 +#define GPIO_AF__PA2_TIM2_CH3 GPIO_AF1_TIM2 +#define GPIO_AF__PA3_TIM2_CH4 GPIO_AF1_TIM2 +#define GPIO_AF__PA5_TIM2_CH1 GPIO_AF1_TIM2 +#define GPIO_AF__PA7_TIM1_CH1N GPIO_AF1_TIM1 +#define GPIO_AF__PA8_TIM1_CH1 GPIO_AF1_TIM1 +#define GPIO_AF__PA9_TIM1_CH2 GPIO_AF1_TIM1 +#define GPIO_AF__PA10_TIM1_CH3 GPIO_AF1_TIM1 +#define GPIO_AF__PA11_TIM1_CH1N GPIO_AF1_TIM1 +#define GPIO_AF__PA15_TIM2_CH1 GPIO_AF1_TIM2 + +#define GPIO_AF__PA0_TIM5_CH1 GPIO_AF2_TIM5 +#define GPIO_AF__PA1_TIM5_CH2 GPIO_AF2_TIM5 +#define GPIO_AF__PA3_TIM5_CH3 GPIO_AF2_TIM5 +#define GPIO_AF__PA4_TIM5_CH4 GPIO_AF2_TIM5 +#define GPIO_AF__PA6_TIM3_CH1 GPIO_AF2_TIM3 +#define GPIO_AF__PA7_TIM3_CH2 GPIO_AF2_TIM3 + +#define GPIO_AF__PA2_TIM9_CH1 GPIO_AF3_TIM9 +#define GPIO_AF__PA3_TIM9_CH2 GPIO_AF3_TIM9 +#define GPIO_AF__PA5_TIM8_CH1N GPIO_AF3_TIM8 +#define GPIO_AF__PA7_TIM8_CH1N GPIO_AF3_TIM8 + +#define GPIO_AF__PA6_TIM13_CH1 GPIO_AF9_TIM13 +#define GPIO_AF__PA7_TIM14_CH1 GPIO_AF9_TIM14 + +//PORTB +#define GPIO_AF__PB0_TIM1_CH2N GPIO_AF1_TIM1 +#define GPIO_AF__PB1_TIM1_CH2N GPIO_AF1_TIM1 +#define GPIO_AF__PB3_TIM2_CH2 GPIO_AF1_TIM2 +#define GPIO_AF__PB10_TIM2_CH3 GPIO_AF1_TIM2 +#define GPIO_AF__PB11_TIM2_CH4 GPIO_AF1_TIM2 +#define GPIO_AF__PB13_TIM1_CH1N GPIO_AF1_TIM1 +#define GPIO_AF__PB14_TIM1_CH2N GPIO_AF1_TIM1 +#define GPIO_AF__PB15_TIM1_CH3N GPIO_AF1_TIM1 + +#define GPIO_AF__PB0_TIM3_CH3 GPIO_AF2_TIM3 +#define GPIO_AF__PB1_TIM3_CH4 GPIO_AF2_TIM3 +#define GPIO_AF__PB4_TIM3_CH1 GPIO_AF2_TIM3 +#define GPIO_AF__PB5_TIM3_CH2 GPIO_AF2_TIM3 +#define GPIO_AF__PB6_TIM4_CH1 GPIO_AF2_TIM4 +#define GPIO_AF__PB7_TIM4_CH2 GPIO_AF2_TIM4 +#define GPIO_AF__PB8_TIM4_CH3 GPIO_AF2_TIM4 +#define GPIO_AF__PB9_TIM4_CH4 GPIO_AF2_TIM4 + +#define GPIO_AF__PB0_TIM8_CH2N GPIO_AF3_TIM8 +#define GPIO_AF__PB1_TIM8_CH3N GPIO_AF3_TIM8 +#define GPIO_AF__PB8_TIM10_CH1 GPIO_AF3_TIM10 +#define GPIO_AF__PB9_TIM11_CH1 GPIO_AF3_TIM11 +#define GPIO_AF__PB14_TIM8_CH2N GPIO_AF3_TIM8 +#define GPIO_AF__PB15_TIM8_CH3N GPIO_AF3_TIM8 + +#define GPIO_AF__PB14_TIM12_CH1 GPIO_AF9_TIM12 +#define GPIO_AF__PB15_TIM12_CH2 GPIO_AF9_TIM12 + +//PORTC +#define GPIO_AF__PC6_TIM3_CH1 GPIO_AF2_TIM3 +#define GPIO_AF__PC7_TIM3_CH2 GPIO_AF2_TIM3 +#define GPIO_AF__PC8_TIM3_CH3 GPIO_AF2_TIM3 +#define GPIO_AF__PC9_TIM3_CH4 GPIO_AF2_TIM3 + +#define GPIO_AF__PC6_TIM8_CH1 GPIO_AF3_TIM8 +#define GPIO_AF__PC7_TIM8_CH2 GPIO_AF3_TIM8 +#define GPIO_AF__PC8_TIM8_CH3 GPIO_AF3_TIM8 +#define GPIO_AF__PC9_TIM8_CH4 GPIO_AF3_TIM8 + +//PORTD +#define GPIO_AF__PD12_TIM4_CH1 GPIO_AF2_TIM4 +#define GPIO_AF__PD13_TIM4_CH2 GPIO_AF2_TIM4 +#define GPIO_AF__PD14_TIM4_CH3 GPIO_AF2_TIM4 +#define GPIO_AF__PD15_TIM4_CH4 GPIO_AF2_TIM4 + +//PORTE +#define GPIO_AF__PE8_TIM1_CH1N GPIO_AF1_TIM1 +#define GPIO_AF__PE9_TIM1_CH1 GPIO_AF1_TIM1 +#define GPIO_AF__PE10_TIM1_CH2N GPIO_AF1_TIM1 +#define GPIO_AF__PE11_TIM1_CH2 GPIO_AF1_TIM1 +#define GPIO_AF__PE12_TIM1_CH3N GPIO_AF1_TIM1 +#define GPIO_AF__PE13_TIM1_CH3 GPIO_AF1_TIM1 +#define GPIO_AF__PE14_TIM1_CH4 GPIO_AF1_TIM1 + +#define GPIO_AF__PE5_TIM9_CH1 GPIO_AF3_TIM9 +#define GPIO_AF__PE6_TIM9_CH2 GPIO_AF3_TIM9 + +//PORTF +#define GPIO_AF__PF6_TIM10_CH1 GPIO_AF3_TIM10 +#define GPIO_AF__PF7_TIM11_CH1 GPIO_AF3_TIM11 + +//PORTH +#define GPIO_AF__PH10_TIM5_CH1 GPIO_AF2_TIM5 +#define GPIO_AF__PH11_TIM5_CH2 GPIO_AF2_TIM5 +#define GPIO_AF__PH12_TIM5_CH3 GPIO_AF2_TIM5 + +#define GPIO_AF__PH13_TIM8_CH1N GPIO_AF3_TIM8 +#define GPIO_AF__PH14_TIM8_CH2N GPIO_AF3_TIM8 +#define GPIO_AF__PH15_TIM8_CH3N GPIO_AF3_TIM8 + +#define GPIO_AF__PH6_TIM12_CH1 GPIO_AF9_TIM12 +#define GPIO_AF__PH9_TIM12_CH2 GPIO_AF9_TIM12 + +//PORTI +#define GPIO_AF__PI0_TIM5_CH4 GPIO_AF2_TIM5 + +#define GPIO_AF__PI2_TIM8_CH4 GPIO_AF3_TIM8 +#define GPIO_AF__PI5_TIM8_CH1 GPIO_AF3_TIM8 +#define GPIO_AF__PI6_TIM8_CH2 GPIO_AF3_TIM8 +#define GPIO_AF__PI7_TIM8_CH3 GPIO_AF3_TIM8 + #endif /**** Common Defines across all targets ****/ @@ -432,6 +718,16 @@ #define DMA_NONE_HANDLER 0 +#if defined(STM32F7) +#define DEF_CHAN_CH1 TIM_CHANNEL_1 +#define DEF_CHAN_CH2 TIM_CHANNEL_2 +#define DEF_CHAN_CH3 TIM_CHANNEL_3 +#define DEF_CHAN_CH4 TIM_CHANNEL_4 +#define DEF_CHAN_CH1N TIM_CHANNEL_1 +#define DEF_CHAN_CH2N TIM_CHANNEL_2 +#define DEF_CHAN_CH3N TIM_CHANNEL_3 +#define DEF_CHAN_CH4N TIM_CHANNEL_4 +#else #define DEF_CHAN_CH1 TIM_Channel_1 #define DEF_CHAN_CH2 TIM_Channel_2 #define DEF_CHAN_CH3 TIM_Channel_3 @@ -440,6 +736,7 @@ #define DEF_CHAN_CH2N TIM_Channel_2 #define DEF_CHAN_CH3N TIM_Channel_3 #define DEF_CHAN_CH4N TIM_Channel_4 +#endif #define DEF_CHAN_CH1_OUTPUT TIMER_OUTPUT_NONE #define DEF_CHAN_CH2_OUTPUT TIMER_OUTPUT_NONE @@ -463,4 +760,4 @@ #define DMA2_CH4_CHANNEL DMA2_Channel4 #define DMA2_CH5_CHANNEL DMA2_Channel5 #define DMA2_CH6_CHANNEL DMA2_Channel6 -#define DMA2_CH7_CHANNEL DMA2_Channel7 \ No newline at end of file +#define DMA2_CH7_CHANNEL DMA2_Channel7 diff --git a/src/main/target/ANYFCF7/target.c b/src/main/target/ANYFCF7/target.c index f05f3ceea..b2a5a909a 100644 --- a/src/main/target/ANYFCF7/target.c +++ b/src/main/target/ANYFCF7/target.c @@ -19,72 +19,72 @@ #include #include "drivers/io.h" -#include "drivers/dma.h" +#include "drivers/dma.h" #include "drivers/timer.h" +#include "drivers/timer_def.h" #if defined(USE_DSHOT) // DSHOT TEST const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM12, IO_TAG(PB14), TIM_CHANNEL_1, TIM_USE_PPM | TIM_USE_PWM, 0, GPIO_AF9_TIM12, NULL, 0, 0 }, // S1_IN - { TIM12, IO_TAG(PB15), TIM_CHANNEL_2, TIM_USE_PWM, 0, GPIO_AF9_TIM12, NULL, 0, 0 }, // S2_IN - { TIM8, IO_TAG(PC6), TIM_CHANNEL_1, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S3_IN - { TIM8, IO_TAG(PC7), TIM_CHANNEL_2, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S4_IN - { TIM8, IO_TAG(PC9), TIM_CHANNEL_4, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S5_IN - { TIM8, IO_TAG(PC8), TIM_CHANNEL_3, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S6_IN + DEF_TIM(TIM12, CH1, PB14, TIM_USE_PWM | TIM_USE_PPM, 0, 0 ), // S1_IN + DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM, 0, 0 ), // S2_IN + DEF_TIM(TIM8, CH1, PC6, TIM_USE_PWM, 0, 0 ), // S3_IN + DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM, 0, 0 ), // S4_IN + DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0 ), // S5_IN + DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0 ), // S6_IN - { TIM4, IO_TAG(PB8), TIM_CHANNEL_3, TIM_USE_MOTOR, 1, GPIO_AF2_TIM4, DMA1_Stream7, DMA_CHANNEL_2, DMA1_ST7_HANDLER }, // S10_OUT 1 - { TIM2, IO_TAG(PA2), TIM_CHANNEL_3, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, DMA1_Stream1, DMA_CHANNEL_3, DMA1_ST1_HANDLER }, // S6_OUT 2 - { TIM2, IO_TAG(PA3), TIM_CHANNEL_4, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, DMA1_Stream6, DMA_CHANNEL_3, DMA1_ST6_HANDLER }, // S1_OUT 4 - { TIM5, IO_TAG(PA1), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF2_TIM5, DMA1_Stream4, DMA_CHANNEL_6, DMA1_ST4_HANDLER }, // S2_OUT - { TIM3, IO_TAG(PB5), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF2_TIM3, DMA1_Stream5, DMA_CHANNEL_5, DMA1_ST5_HANDLER }, // S4_OUT - { TIM5, IO_TAG(PA0), TIM_CHANNEL_1, TIM_USE_MOTOR, 1, GPIO_AF2_TIM5, DMA1_Stream2, DMA_CHANNEL_6, DMA1_ST2_HANDLER }, // S7_OUT - { TIM4, IO_TAG(PB9), TIM_CHANNEL_4, TIM_USE_MOTOR, 1, GPIO_AF2_TIM4, NULL, 0, 0 }, // S5_OUT 3 - { TIM9, IO_TAG(PE6), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF3_TIM9, NULL, 0, 0 }, // S3_OUT - { TIM2, IO_TAG(PB3), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, NULL, 0, 0 }, // S8_OUT - { TIM3, IO_TAG(PB4), TIM_CHANNEL_1, TIM_USE_MOTOR, 1, GPIO_AF2_TIM3, NULL, 0, 0 }, // S9_OUT + DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 1, 0 ), // S10_OUT 1 + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 1, 0 ), // S6_OUT 2 + DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 1, 0 ), // S1_OUT 4 + DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR | TIM_USE_LED, 1, 0 ), // S2_OUT + DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 1, 0 ), // S4_OUT + DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 1, 0 ), // S7_OUT + DEF_TIM(TIM4, CH4, PB9, TIM_USE_MOTOR, 1, 0 ), // S5_OUT 3 + DEF_TIM(TIM9, CH2, PE6, TIM_USE_MOTOR, 1, 0 ), // S3_OUT + DEF_TIM(TIM2, CH2, PB3, TIM_USE_MOTOR, 1, 0 ), // S8_OUT + DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 1, 0 ), // S9_OUT }; #else // STANDARD LAYOUT const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { - { TIM12, IO_TAG(PB14), TIM_CHANNEL_1, TIM_USE_PWM | TIM_USE_PPM, 0, GPIO_AF9_TIM12, NULL, 0, 0 }, // S1_IN - { TIM12, IO_TAG(PB15), TIM_CHANNEL_2, TIM_USE_PWM, 0, GPIO_AF9_TIM12, NULL, 0, 0 }, // S2_IN - { TIM8, IO_TAG(PC6), TIM_CHANNEL_1, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S3_IN - { TIM8, IO_TAG(PC7), TIM_CHANNEL_2, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S4_IN - { TIM8, IO_TAG(PC9), TIM_CHANNEL_4, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S5_IN - { TIM8, IO_TAG(PC8), TIM_CHANNEL_3, TIM_USE_PWM, 0, GPIO_AF3_TIM8, NULL, 0, 0 }, // S6_IN + DEF_TIM(TIM12, CH1, PB14, TIM_USE_PWM | TIM_USE_PPM, 0, 0 ), // S1_IN + DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM, 0, 0 ), // S2_IN + DEF_TIM(TIM8, CH1, PC6, TIM_USE_PWM, 0, 0 ), // S3_IN + DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM, 0, 0 ), // S4_IN + DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0 ), // S5_IN + DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0 ), // S6_IN - { TIM4, IO_TAG(PB8), TIM_CHANNEL_3, TIM_USE_MOTOR, 1, GPIO_AF2_TIM4, NULL, 0, 0 }, // S10_OUT 1 - { TIM2, IO_TAG(PA2), TIM_CHANNEL_3, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, NULL, 0, 0 }, // S6_OUT 2 - { TIM4, IO_TAG(PB9), TIM_CHANNEL_4, TIM_USE_MOTOR, 1, GPIO_AF2_TIM4, NULL, 0, 0 }, // S5_OUT 3 - { TIM2, IO_TAG(PA3), TIM_CHANNEL_4, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, NULL, 0, 0 }, // S1_OUT 4 - { TIM5, IO_TAG(PA1), TIM_CHANNEL_2, TIM_USE_MOTOR | TIM_USE_LED, 1, GPIO_AF2_TIM5, DMA1_Stream4, DMA_CHANNEL_6, 0 }, // S2_OUT - { TIM9, IO_TAG(PE6), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF3_TIM9, NULL, 0, 0 }, // S3_OUT - { TIM3, IO_TAG(PB5), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF2_TIM3, NULL, 0, 0 }, // S4_OUT - { TIM5, IO_TAG(PA0), TIM_CHANNEL_1, TIM_USE_MOTOR, 1, GPIO_AF2_TIM5, NULL, 0, 0 }, // S7_OUT - { TIM2, IO_TAG(PB3), TIM_CHANNEL_2, TIM_USE_MOTOR, 1, GPIO_AF1_TIM2, NULL, 0, 0 }, // S8_OUT - { TIM3, IO_TAG(PB4), TIM_CHANNEL_1, TIM_USE_MOTOR, 1, GPIO_AF2_TIM3, NULL, 0, 0 }, // S9_OUT + DEF_TIM(TIM4, CH3, PB8, TIM_USE_MOTOR, 1, 0 ), // S10_OUT 1 + DEF_TIM(TIM2, CH3, PA2, TIM_USE_MOTOR, 1, 0 ), // S6_OUT 2 + DEF_TIM(TIM4, CH4, PB9, TIM_USE_MOTOR, 1, 0 ), // S5_OUT 3 + DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 1, 0 ), // S1_OUT 4 + DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR | TIM_USE_LED, 1, 0 ), // S2_OUT + DEF_TIM(TIM9, CH2, PE6, TIM_USE_MOTOR, 1, 0 ), // S3_OUT + DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 1, 0 ), // S4_OUT + DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 1, 0 ), // S7_OUT + DEF_TIM(TIM2, CH2, PB3, TIM_USE_MOTOR, 1, 0 ), // S8_OUT + DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 1, 0 ), // S9_OUT }; #endif - // ALTERNATE LAYOUT //const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = { -// { TIM12, IO_TAG(PB14), TIM_CHANNEL_1, TIM8_BRK_TIM12_IRQn, 0, IOCFG_AF_PP , GPIO_AF9_TIM12}, // S1_IN -// { TIM12, IO_TAG(PB15), TIM_CHANNEL_2, TIM8_BRK_TIM12_IRQn, 0, IOCFG_AF_PP , GPIO_AF9_TIM12}, // S2_IN -// { TIM8, IO_TAG(PC6), TIM_CHANNEL_1, TIM8_CC_IRQn, 0, IOCFG_AF_PP , GPIO_AF3_TIM8}, // S3_IN -// { TIM8, IO_TAG(PC7), TIM_CHANNEL_2, TIM8_CC_IRQn, 0, IOCFG_AF_PP , GPIO_AF3_TIM8}, // S4_IN -// { TIM8, IO_TAG(PC9), TIM_CHANNEL_4, TIM8_CC_IRQn, 0, IOCFG_AF_PP , GPIO_AF3_TIM8}, // S5_IN -// { TIM8, IO_TAG(PC8), TIM_CHANNEL_3, TIM8_CC_IRQn, 0, IOCFG_AF_PP , GPIO_AF3_TIM8}, // S6_IN +// DEF_TIM(TIM12, CH1, PB14, TIM_USE_PWM | TIM_USE_PPM, 0, 0 ), // S1_IN +// DEF_TIM(TIM12, CH2, PB15, TIM_USE_PWM, 0, 0 ), // S2_IN +// DEF_TIM(TIM8, CH1, PC6, TIM_USE_PWM, 0, 0 ), // S3_IN +// DEF_TIM(TIM8, CH2, PC7, TIM_USE_PWM, 0, 0 ), // S4_IN +// DEF_TIM(TIM8, CH4, PC9, TIM_USE_PWM, 0, 0 ), // S5_IN +// DEF_TIM(TIM8, CH3, PC8, TIM_USE_PWM, 0, 0 ), // S6_IN // -// { TIM10, IO_TAG(PB8), TIM_CHANNEL_1, TIM1_UP_TIM10_IRQn, 1, IOCFG_AF_PP , GPIO_AF3_TIM10}, // S10_OUT -// { TIM9, IO_TAG(PA2), TIM_CHANNEL_1, TIM1_BRK_TIM9_IRQn, 1, IOCFG_AF_PP , GPIO_AF3_TIM9}, // S6_OUT -// { TIM2, IO_TAG(PA3), TIM_CHANNEL_4, TIM2_IRQn, 1, IOCFG_AF_PP , GPIO_AF1_TIM2}, // S1_OUT -// { TIM11, IO_TAG(PB9), TIM_CHANNEL_1, TIM1_TRG_COM_TIM11_IRQn, 1, IOCFG_AF_PP , GPIO_AF3_TIM11}, // S5_OUT -// { TIM5, IO_TAG(PA1), TIM_CHANNEL_2, TIM5_IRQn, 1, IOCFG_AF_PP , GPIO_AF2_TIM5}, // S2_OUT -// { TIM9, IO_TAG(PE6), TIM_CHANNEL_2, TIM1_BRK_TIM9_IRQn, 1, IOCFG_AF_PP , GPIO_AF3_TIM9}, // S3_OUT -// { TIM3, IO_TAG(PB5), TIM_CHANNEL_2, TIM3_IRQn, 1, IOCFG_AF_PP , GPIO_AF2_TIM3}, // S4_OUT -// { TIM5, IO_TAG(PA0), TIM_CHANNEL_1, TIM5_IRQn, 1, IOCFG_AF_PP , GPIO_AF2_TIM5}, // S7_OUT -// { TIM2, IO_TAG(PB3), TIM_CHANNEL_2, TIM2_IRQn, 1, IOCFG_AF_PP , GPIO_AF1_TIM2}, // S8_OUT -// { TIM3, IO_TAG(PB4), TIM_CHANNEL_1, TIM3_IRQn, 1, IOCFG_AF_PP , GPIO_AF2_TIM3}, // S9_OUT +// DEF_TIM(TIM10, CH1, PB8, TIM_USE_MOTOR, 1, 0 ), // S10_OUT 1 +// DEF_TIM(TIM9, CH1, PA2, TIM_USE_MOTOR, 1, 0 ), // S6_OUT 2 +// DEF_TIM(TIM11, CH1, PB9, TIM_USE_MOTOR, 1, 0 ), // S5_OUT 3 +// DEF_TIM(TIM2, CH4, PA3, TIM_USE_MOTOR, 1, 0 ), // S1_OUT 4 +// DEF_TIM(TIM5, CH2, PA1, TIM_USE_MOTOR | TIM_USE_LED, 1, 0 ), // S2_OUT +// DEF_TIM(TIM9, CH2, PE6, TIM_USE_MOTOR, 1, 0 ), // S3_OUT +// DEF_TIM(TIM3, CH2, PB5, TIM_USE_MOTOR, 1, 0 ), // S4_OUT +// DEF_TIM(TIM5, CH1, PA0, TIM_USE_MOTOR, 1, 0 ), // S7_OUT +// DEF_TIM(TIM2, CH2, PB3, TIM_USE_MOTOR, 1, 0 ), // S8_OUT +// DEF_TIM(TIM3, CH1, PB4, TIM_USE_MOTOR, 1, 0 ), // S9_OUT //};