Added preliminary support for STM32F765xx
This commit is contained in:
Andrey Mironov
parent
e2b91ae0f1
commit
7a331d03f4
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@ -127,7 +127,12 @@ endif
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ARCH_FLAGS = -mthumb -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -fsingle-precision-constant -Wdouble-promotion
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DEVICE_FLAGS = -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER
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ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XG_TARGETS)))
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ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XI_TARGETS)))
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DEVICE_FLAGS += -DSTM32F765xx
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LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f765.ld
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STARTUP_SRC = startup_stm32f765xx.s
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TARGET_FLASH = 2048
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else ifeq ($(TARGET),$(filter $(TARGET),$(F7X5XG_TARGETS)))
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DEVICE_FLAGS += -DSTM32F745xx
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LD_SCRIPT = $(LINKER_DIR)/stm32_flash_f74x.ld
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STARTUP_SRC = startup_stm32f745xx.s
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@ -31,6 +31,7 @@ extern uint8_t __config_start; // configured via linker script when building b
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extern uint8_t __config_end;
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#endif
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// @todo this is not strictly correct for F4/F7, where sector sizes are variable
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#if !defined(FLASH_PAGE_SIZE)
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// F1
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# if defined(STM32F10X_MD)
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@ -56,6 +57,8 @@ extern uint8_t __config_end;
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# define FLASH_PAGE_SIZE ((uint32_t)0x8000) // 32K sectors
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# elif defined(STM32F746xx)
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# define FLASH_PAGE_SIZE ((uint32_t)0x8000)
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# elif defined(STM32F765xx)
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# define FLASH_PAGE_SIZE ((uint32_t)0x8000)
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# elif defined(UNIT_TEST)
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# define FLASH_PAGE_SIZE (0x400)
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// SIMULATOR
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@ -101,7 +104,7 @@ void config_streamer_start(config_streamer_t *c, uintptr_t base, int size)
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c->err = 0;
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}
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#if defined(STM32F745xx) || defined(STM32F746xx)
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#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx)
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/*
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Sector 0 0x08000000 - 0x08007FFF 32 Kbytes
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Sector 1 0x08008000 - 0x0800FFFF 32 Kbytes
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@ -111,6 +114,12 @@ Sector 4 0x08020000 - 0x0803FFFF 128 Kbytes
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Sector 5 0x08040000 - 0x0807FFFF 256 Kbytes
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Sector 6 0x08080000 - 0x080BFFFF 256 Kbytes
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Sector 7 0x080C0000 - 0x080FFFFF 256 Kbytes
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F7X5XI device with 2M flash
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Sector 8 0x08100000 - 0x0813FFFF 256 Kbytes
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Sector 9 0x08140000 - 0x0817FFFF 256 Kbytes
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Sector 10 0x08180000 - 0x081BFFFF 256 Kbytes
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Sector 11 0x081C0000 - 0x081FFFFF 256 Kbytes
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*/
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static uint32_t getFLASHSectorForEEPROM(void)
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@ -131,6 +140,16 @@ static uint32_t getFLASHSectorForEEPROM(void)
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return FLASH_SECTOR_6;
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if ((uint32_t)&__config_start <= 0x080FFFFF)
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return FLASH_SECTOR_7;
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#if defined(STM32F765xx)
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if ((uint32_t)&__config_start <= 0x0813FFFF)
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return FLASH_SECTOR_8;
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if ((uint32_t)&__config_start <= 0x0817FFFF)
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return FLASH_SECTOR_9;
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if ((uint32_t)&__config_start <= 0x081BFFFF)
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return FLASH_SECTOR_10;
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if ((uint32_t)&__config_start <= 0x081FFFFF)
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return FLASH_SECTOR_11;
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#endif
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// Not good
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while (1) {
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@ -58,9 +58,8 @@
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#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
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// These addresses are incorrectly defined in stm32f7xx_ll_adc.h
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#if defined(STM32F745xx) || defined(STM32F746xx)
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// F745xx_F746xx
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#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx)
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// F745xx_F746xx and F765xx_F767xx_F769xx
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#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A))
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#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C))
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#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E))
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@ -26,7 +26,7 @@
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#pragma GCC poison sprintf snprintf
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#endif
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#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F722xx)
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#if defined(STM32F765xx) || defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F722xx)
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#include "stm32f7xx.h"
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#include "stm32f7xx_hal.h"
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#include "system_stm32f7xx.h"
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@ -0,0 +1,654 @@
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/**
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******************************************************************************
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* @file startup_stm32f765xx.s
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* @author MCD Application Team
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* @version V1.2.0
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* @date 30-December-2016
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* @brief STM32F765xx Devices vector table for GCC based toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M7 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m7
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* start address for the .fastram_bss section. defined in linker script */
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.word _sfastram_bss
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/* end address for the .fastram_bss section. defined in linker script */
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.word _efastram_bss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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ldr r2, =_ssram2
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b LoopFillZerosram2
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/* Zero fill the sram2 segment. */
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FillZerosram2:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerosram2:
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ldr r3, = _esram2
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cmp r2, r3
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bcc FillZerosram2
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ldr r2, =_sfastram_bss
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b LoopFillZerofastram_bss
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/* Zero fill the fastram_bss segment. */
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FillZerofastram_bss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerofastram_bss:
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ldr r3, = _efastram_bss
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cmp r2, r3
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bcc FillZerofastram_bss
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/* Call the clock system initialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M7. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_IRQHandler /* PVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word CAN1_TX_IRQHandler /* CAN1 TX */
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.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
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.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.word CAN1_SCE_IRQHandler /* CAN1 SCE */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_IRQHandler /* USART3 */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word FMC_IRQHandler /* FMC */
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.word SDMMC1_IRQHandler /* SDMMC1 */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word UART4_IRQHandler /* UART4 */
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.word UART5_IRQHandler /* UART5 */
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.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
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.word TIM7_IRQHandler /* TIM7 */
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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.word ETH_IRQHandler /* Ethernet */
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.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
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.word CAN2_TX_IRQHandler /* CAN2 TX */
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.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
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.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
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.word CAN2_SCE_IRQHandler /* CAN2 SCE */
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.word OTG_FS_IRQHandler /* USB OTG FS */
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.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
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.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
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.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
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.word USART6_IRQHandler /* USART6 */
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.word I2C3_EV_IRQHandler /* I2C3 event */
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.word I2C3_ER_IRQHandler /* I2C3 error */
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.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
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.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
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.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
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.word OTG_HS_IRQHandler /* USB OTG HS */
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.word DCMI_IRQHandler /* DCMI */
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.word 0 /* Reserved */
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.word RNG_IRQHandler /* RNG */
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.word FPU_IRQHandler /* FPU */
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.word UART7_IRQHandler /* UART7 */
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.word UART8_IRQHandler /* UART8 */
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.word SPI4_IRQHandler /* SPI4 */
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.word SPI5_IRQHandler /* SPI5 */
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.word SPI6_IRQHandler /* SPI6 */
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.word SAI1_IRQHandler /* SAI1 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word DMA2D_IRQHandler /* DMA2D */
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.word SAI2_IRQHandler /* SAI2 */
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.word QUADSPI_IRQHandler /* QUADSPI */
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.word LPTIM1_IRQHandler /* LPTIM1 */
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.word CEC_IRQHandler /* HDMI_CEC */
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.word I2C4_EV_IRQHandler /* I2C4 Event */
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.word I2C4_ER_IRQHandler /* I2C4 Error */
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.word SPDIF_RX_IRQHandler /* SPDIF_RX */
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.word 0 /* Reserved */
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.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
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.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
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.word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
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.word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
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.word SDMMC2_IRQHandler /* SDMMC2 */
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.word CAN3_TX_IRQHandler /* CAN3 TX */
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.word CAN3_RX0_IRQHandler /* CAN3 RX0 */
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.word CAN3_RX1_IRQHandler /* CAN3 RX1 */
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.word CAN3_SCE_IRQHandler /* CAN3 SCE */
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.word 0 /* Reserved */
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.word MDIOS_IRQHandler /* MDIOS */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_TX_IRQHandler
|
||||
.thumb_set CAN3_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_RX0_IRQHandler
|
||||
.thumb_set CAN3_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_RX1_IRQHandler
|
||||
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_SCE_IRQHandler
|
||||
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32_flash_f765.ld
|
||||
**
|
||||
** Abstract : Linker script for STM32F765xITx Device with
|
||||
** 2048KByte FLASH, 512KByte RAM
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/*
|
||||
0x00000000 to 0x00003FFF 16K TCM RAM,
|
||||
|
||||
0x08000000 to 0x081FFFFF 2048K full flash,
|
||||
0x08000000 to 0x08007FFF 32K isr vector, startup code,
|
||||
0x08008000 to 0x0800FFFF 32K config,
|
||||
0x08010000 to 0x081FFFFF 1984K firmware,
|
||||
*/
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
ITCM_RAM (rx) : ORIGIN = 0x00000000, LENGTH = 16K
|
||||
|
||||
ITCM_FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 32K
|
||||
ITCM_FLASH_CONFIG (r) : ORIGIN = 0x00208000, LENGTH = 32K
|
||||
ITCM_FLASH1 (rx) : ORIGIN = 0x00210000, LENGTH = 1984K
|
||||
|
||||
AXIM_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||
AXIM_FLASH_CONFIG (r) : ORIGIN = 0x08008000, LENGTH = 32K
|
||||
AXIM_FLASH1 (rx) : ORIGIN = 0x08010000, LENGTH = 1984K
|
||||
|
||||
DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
SRAM1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K
|
||||
SRAM2 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
|
||||
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
|
||||
}
|
||||
|
||||
REGION_ALIAS("FLASH", AXIM_FLASH)
|
||||
REGION_ALIAS("FLASH_CONFIG", AXIM_FLASH_CONFIG)
|
||||
REGION_ALIAS("FLASH1", AXIM_FLASH1)
|
||||
|
||||
REGION_ALIAS("STACKRAM", DTCM_RAM)
|
||||
REGION_ALIAS("FASTRAM", DTCM_RAM)
|
||||
REGION_ALIAS("RAM", DTCM_RAM)
|
||||
|
||||
INCLUDE "stm32_flash_f7_split.ld"
|
||||
Loading…
Reference in New Issue