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STM32H750 - Apply workaround to the SDMMC Errata 2.11.4 

Issue: "Consecutive multiple block transfers can induce incorrect data length"
Workaround: "8 SDMMC clock cycles must elapse before DTEN can be set."
This commit is contained in:
Dominic Clifton 2019-02-22 15:22:43 +01:00 committed by jflyper
parent adcf556ea5
commit 844683279a
1 changed files with 11 additions and 0 deletions
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11
lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
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@ -464,6 +464,17 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef*
Data->TransferMode |\ Data->TransferMode |\
Data->DPSM); Data->DPSM);
// DC - See errata 2.11.4 - 8 SDMMC clock cycles must elapse before DTEN can be set.
// 32U below is used as a VERY rough guess that the SDMMC clock is 1/4 of the sytem clock, 8 * 4 = 32 and that the
// assembly below only takes 1 CPU cycle to run. All of which will be wrong, but right enough most of the time, especially
// when considering other processing overheads.
register uint32_t count = 32U;
do
{
count--;
} while(count > 0);
// DC - See errata 2.11.4
/* Write to SDMMC DCTRL */ /* Write to SDMMC DCTRL */
MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);