rusefi
/
atbetaflight
mirror of https://github.com/rusefi/atbetaflight.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #5279 from betaflight/cf-changes-4 

CF/BF - Enable RTC6705 power control.
This commit is contained in:
Michael Keller 2018-03-04 01:08:08 +13:00 committed by GitHub
parent dedad2f920 4901b947e3
commit 9e90f9a635
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 31 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/main/drivers/vtx_rtc6705_soft_spi.c
View File

@ -46,25 +46,42 @@
#define DISABLE_RTC6705 IOHi(rtc6705CsnPin)
#define ENABLE_RTC6705 IOLo(rtc6705CsnPin)
#ifdef RTC6705_POWER_PIN
static IO_t vtxPowerPin = IO_NONE;
#endif
#define ENABLE_VTX_POWER() IOLo(vtxPowerPin)
#define DISABLE_VTX_POWER() IOHi(vtxPowerPin)
static IO_t rtc6705DataPin = IO_NONE;
static IO_t rtc6705CsnPin = IO_NONE;
static IO_t rtc6705ClkPin = IO_NONE;
void rtc6705IOInit(void)
{
rtc6705DataPin = IOGetByTag(IO_TAG(RTC6705_SPI_MOSI_PIN));
rtc6705ClkPin = IOGetByTag(IO_TAG(RTC6705_SPICLK_PIN));
rtc6705CsnPin = IOGetByTag(IO_TAG(RTC6705_CS_PIN));
#ifdef RTC6705_POWER_PIN
vtxPowerPin = IOGetByTag(IO_TAG(RTC6705_POWER_PIN));
IOInit(vtxPowerPin, OWNER_VTX, 0);
IOInit(rtc6705CsnPin, OWNER_SPI_CS, RESOURCE_SOFT_OFFSET);
IOConfigGPIO(rtc6705CsnPin, IOCFG_OUT_PP);
DISABLE_RTC6705;
DISABLE_VTX_POWER();
IOConfigGPIO(vtxPowerPin, IOCFG_OUT_PP);
#endif
rtc6705DataPin = IOGetByTag(IO_TAG(RTC6705_SPI_MOSI_PIN));
rtc6705CsnPin = IOGetByTag(IO_TAG(RTC6705_CS_PIN));
rtc6705ClkPin = IOGetByTag(IO_TAG(RTC6705_SPICLK_PIN));
IOInit(rtc6705DataPin, OWNER_SPI_MOSI, RESOURCE_SOFT_OFFSET);
IOConfigGPIO(rtc6705DataPin, IOCFG_OUT_PP);
IOInit(rtc6705ClkPin, OWNER_SPI_SCK, RESOURCE_SOFT_OFFSET);
IOConfigGPIO(rtc6705ClkPin, IOCFG_OUT_PP);
// Important: The order of GPIO configuration calls are critical to ensure that incorrect signals are not briefly sent to the VTX.
// GPIO bit is enabled so here so the CS/LE pin output is not pulled low when the GPIO is set in output mode.
DISABLE_RTC6705;
IOInit(rtc6705CsnPin, OWNER_SPI_CS, RESOURCE_SOFT_OFFSET);
IOConfigGPIO(rtc6705CsnPin, IOCFG_OUT_PP);
}
static void rtc6705_write_register(uint8_t addr, uint32_t data)
@ -121,10 +138,17 @@ void rtc6705SetRFPower(uint8_t rf_power)
void rtc6705Disable(void)
{
#ifdef RTC6705_POWER_PIN
DISABLE_VTX_POWER();
#endif
}
void rtc6705Enable(void)
{
#ifdef RTC6705_POWER_PIN
ENABLE_VTX_POWER();
#endif
}
#endif

2
src/main/fc/fc_init.c
View File

@ -238,7 +238,7 @@ void spiPreInit(void)
#ifdef USE_MAG_SPI_AK8963
spiPreInitCs(IO_TAG(AK8963_CS_PIN));
#endif
#if defined(USE_VTX_RTC6705)
#if defined(RTC6705_CS_PIN) && !defined(USE_VTX_RTC6705_SOFTSPI) // RTC6705 soft SPI initialisation handled elsewhere.
spiPreInitCs(IO_TAG(RTC6705_CS_PIN));
#endif
#ifdef USE_FLASH_M25P16