Add W25Q128FV driver (QSPI only)
* Enable QSPI flash chip drivers on NUCLEOH743 for some CI visibility. * Rework QSPI flash detection. * Supports chips that are in QSPI mode by default (factory). * Supports chips that are in QSPI mode due to configuration (e.g. Quad Enable in Non-Volatile on W25Q128FV) * Supports chips that need 8 dummy bytes (e.g. W25Q128JV) and ones that don't (e.g. W25N01G)
This commit is contained in:
Dominic Clifton
Dominic Clifton
parent
2a5e457603
commit
c8e741bd18
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@ -406,6 +406,7 @@ SRC += \
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drivers/flash.c \
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drivers/flash_m25p16.c \
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drivers/flash_w25n01g.c \
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drivers/flash_w25q128fv.c \
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drivers/flash_w25m.c \
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io/flashfs.c \
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$(MSC_SRC)
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@ -109,12 +109,14 @@ void quadSpiSetDivisor(QUADSPI_TypeDef *instance, uint16_t divisor);
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bool quadSpiTransmit1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, const uint8_t *out, int length);
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bool quadSpiReceive1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint8_t *in, int length);
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bool quadSpiReceive4LINES(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint8_t *in, int length);
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bool quadSpiInstructionWithData1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, const uint8_t *out, int length);
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bool quadSpiReceiveWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, uint8_t *in, int length);
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bool quadSpiReceiveWithAddress4LINES(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, uint8_t *in, int length);
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bool quadSpiTransmitWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, const uint8_t *out, int length);
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bool quadSpiTransmitWithAddress4LINES(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, const uint8_t *out, int length);
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bool quadSpiInstructionWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize);
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@ -286,6 +286,44 @@ bool quadSpiReceive1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t
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return true;
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}
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bool quadSpiReceive4LINES(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint8_t *in, int length)
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{
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QUADSPIDevice device = quadSpiDeviceByInstance(instance);
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HAL_StatusTypeDef status;
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QSPI_CommandTypeDef cmd;
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cmd.InstructionMode = QSPI_INSTRUCTION_4_LINES;
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cmd.AddressMode = QSPI_ADDRESS_NONE;
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cmd.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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cmd.DataMode = QSPI_DATA_4_LINES;
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cmd.DummyCycles = dummyCycles;
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cmd.DdrMode = QSPI_DDR_MODE_DISABLE;
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cmd.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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cmd.Instruction = instruction;
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cmd.NbData = length;
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quadSpiSelectDevice(instance);
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status = HAL_QSPI_Command(&quadSpiDevice[device].hquadSpi, &cmd, QUADSPI_DEFAULT_TIMEOUT);
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bool timeout = (status != HAL_OK);
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if (!timeout) {
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status = HAL_QSPI_Receive(&quadSpiDevice[device].hquadSpi, in, QUADSPI_DEFAULT_TIMEOUT);
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timeout = (status != HAL_OK);
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}
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quadSpiDeselectDevice(instance);
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if (timeout) {
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quadSpiTimeoutUserCallback(instance);
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return false;
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}
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return true;
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}
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bool quadSpiReceiveWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, uint8_t *in, int length)
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{
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QUADSPIDevice device = quadSpiDeviceByInstance(instance);
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@ -404,6 +442,46 @@ bool quadSpiTransmitWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruct
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return true;
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}
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bool quadSpiTransmitWithAddress4LINES(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize, const uint8_t *out, int length)
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{
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QUADSPIDevice device = quadSpiDeviceByInstance(instance);
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HAL_StatusTypeDef status;
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QSPI_CommandTypeDef cmd;
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cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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cmd.AddressMode = QSPI_ADDRESS_1_LINE;
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cmd.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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cmd.DataMode = QSPI_DATA_4_LINES;
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cmd.DummyCycles = dummyCycles;
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cmd.DdrMode = QSPI_DDR_MODE_DISABLE;
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cmd.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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cmd.Instruction = instruction;
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cmd.Address = address;
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cmd.AddressSize = quadSpi_addressSizeFromValue(addressSize);
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cmd.NbData = length;
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quadSpiSelectDevice(instance);
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status = HAL_QSPI_Command(&quadSpiDevice[device].hquadSpi, &cmd, QUADSPI_DEFAULT_TIMEOUT);
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bool timeout = (status != HAL_OK);
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if (!timeout) {
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status = HAL_QSPI_Transmit(&quadSpiDevice[device].hquadSpi, (uint8_t *)out, QUADSPI_DEFAULT_TIMEOUT);
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timeout = (status != HAL_OK);
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}
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quadSpiDeselectDevice(instance);
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if (timeout) {
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quadSpiTimeoutUserCallback(instance);
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return false;
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}
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return true;
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}
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bool quadSpiInstructionWithAddress1LINE(QUADSPI_TypeDef *instance, uint8_t instruction, uint8_t dummyCycles, uint32_t address, uint8_t addressSize)
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{
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QUADSPIDevice device = quadSpiDeviceByInstance(instance);
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@ -32,6 +32,7 @@
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#include "flash_impl.h"
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#include "flash_m25p16.h"
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#include "flash_w25n01g.h"
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#include "flash_w25q128fv.h"
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#include "flash_w25m.h"
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#include "drivers/bus_spi.h"
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#include "drivers/bus_quadspi.h"
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@ -55,39 +56,72 @@ static int flashPartitions = 0;
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#ifdef USE_QUADSPI
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static bool flashQuadSpiInit(const flashConfig_t *flashConfig)
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{
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QUADSPI_TypeDef *quadSpiInstance = quadSpiInstanceByDevice(QUADSPI_CFG_TO_DEV(flashConfig->quadSpiDevice));
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quadSpiSetDivisor(quadSpiInstance, QUADSPI_CLOCK_INITIALISATION);
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bool detected = false;
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enum { TRY_1LINE = 0, TRY_4LINE, BAIL};
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int phase = TRY_1LINE;
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QUADSPI_TypeDef *hqspi = quadSpiInstanceByDevice(QUADSPI_CFG_TO_DEV(flashConfig->quadSpiDevice));
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do {
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quadSpiSetDivisor(hqspi, QUADSPI_CLOCK_INITIALISATION);
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// 3 bytes for what we need, but some IC's need 8 dummy cycles after the instruction, so read 4 and make two attempts to
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// assemble the chip id from the response.
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uint8_t readIdResponse[4];
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bool status = quadSpiReceive1LINE(quadSpiInstance, FLASH_INSTRUCTION_RDID, 8, readIdResponse, sizeof(readIdResponse));
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bool status = false;
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switch (phase) {
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case TRY_1LINE:
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status = quadSpiReceive1LINE(hqspi, FLASH_INSTRUCTION_RDID, 0, readIdResponse, 4);
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break;
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case TRY_4LINE:
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status = quadSpiReceive4LINES(hqspi, FLASH_INSTRUCTION_RDID, 2, readIdResponse, 3);
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break;
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default:
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break;
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}
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if (!status) {
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return false;
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phase++;
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continue;
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}
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flashDevice.io.handle.quadSpi = hqspi;
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flashDevice.io.mode = FLASHIO_QUADSPI;
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flashDevice.io.handle.quadSpi = quadSpiInstance;
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// Manufacturer, memory type, and capacity
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uint32_t chipID = (readIdResponse[0] << 16) | (readIdResponse[1] << 8) | (readIdResponse[2]);
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quadSpiSetDivisor(hqspi, QUADSPI_CLOCK_ULTRAFAST);
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#if defined(USE_FLASH_W25N01G) || defined(USE_FLASH_W25M02G)
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quadSpiSetDivisor(quadSpiInstance, QUADSPI_CLOCK_ULTRAFAST);
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#if defined(USE_FLASH_W25N01G)
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if (w25n01g_detect(&flashDevice, chipID)) {
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return true;
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for (uint8_t offset = 0; offset <= 1 && !detected; offset++) {
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uint32_t chipID = (readIdResponse[offset + 0] << 16) | (readIdResponse[offset + 1] << 8) | (readIdResponse[offset + 2]);
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if (offset == 0) {
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#ifdef USE_FLASH_W25Q128FV
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if (!detected && w25q128fv_detect(&flashDevice, chipID)) {
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detected = true;
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}
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#endif
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}
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if (offset == 1) {
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#ifdef USE_FLASH_W25N01G
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if (!detected && w25n01g_detect(&flashDevice, chipID)) {
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detected = true;
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}
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#endif
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#if defined(USE_FLASH_W25M02G)
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if (w25m_detect(&flashDevice, chipID)) {
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return true;
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if (!detected && w25m_detect(&flashDevice, chipID)) {
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detected = true;
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}
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#endif
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}
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}
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phase++;
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} while (phase != BAIL && !detected);
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#endif
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return false;
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return detected;
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}
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#endif // USE_QUADSPI
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@ -0,0 +1,438 @@
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/*
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* This file is part of Cleanflight and Betaflight.
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*
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* Cleanflight and Betaflight are free software. You can redistribute
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* this software and/or modify this software under the terms of the
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* GNU General Public License as published by the Free Software
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* Foundation, either version 3 of the License, or (at your option)
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* any later version.
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*
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* Cleanflight and Betaflight are distributed in the hope that they
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software.
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*
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* If not, see <http://www.gnu.org/licenses/>.
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*
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* Author: Dominic Clifton - Initial implementation and testing.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "platform.h"
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#if defined(USE_FLASH_W25Q128FV) && defined(USE_QUADSPI)
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#define USE_FLASH_WRITES_USING_4LINES
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#define USE_FLASH_READS_USING_4LINES
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#include "build/debug.h"
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#include "common/utils.h"
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#include "drivers/flash.h"
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#include "drivers/flash_impl.h"
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#include "drivers/flash_w25q128fv.h"
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#include "drivers/bus_quadspi.h"
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// JEDEC ID
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#define JEDEC_ID_WINBOND_W25Q128FV_SPI 0xEF4018
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#define JEDEC_ID_WINBOND_W25Q128FV_QUADSPI 0xEF6018
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#define JEDEC_ID_WINBOND_W25Q128JV_QUADSPI 0xEF7018
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// Device size parameters
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#define W25Q128FV_PAGE_SIZE 2048
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#define W25Q128FV_PAGES_PER_BLOCK 64
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#define W25Q128FV_BLOCKS_PER_DIE 1024
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#define W25Q128FV_BLOCK_SIZE (W25Q128FV_PAGES_PER_BLOCK * W25Q128FV_PAGE_SIZE)
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// Sizes
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#define W25Q128FV_STATUS_REGISTER_BITS 8
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#define W25Q128FV_ADDRESS_BITS 24
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// Instructions
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#define W25Q128FV_INSTRUCTION_RDID 0x9F
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#define W25Q128FV_INSTRUCTION_ENABLE_RESET 0x66
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#define W25Q128FV_INSTRUCTION_RESET_DEVICE 0x99
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#define W25Q128FV_INSTRUCTION_READ_STATUS1_REG 0x05
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#define W25Q128FV_INSTRUCTION_READ_STATUS2_REG 0x35
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#define W25Q128FV_INSTRUCTION_READ_STATUS3_REG 0x15
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#define W25Q128FV_INSTRUCTION_WRITE_STATUS1_REG 0x01
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#define W25Q128FV_INSTRUCTION_WRITE_STATUS2_REG 0x31
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#define W25Q128FV_INSTRUCTION_WRITE_STATUS3_REG 0x11
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#define W25Q128FV_INSTRUCTION_WRITE_ENABLE 0x06
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#define W25Q128FV_INSTRUCTION_VOLATILE_WRITE_ENABLE 0x50
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#define W25Q128FV_INSTRUCTION_BLOCK_ERASE_64KB 0xD8
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#define W25Q128FV_INSTRUCTION_CHIP_ERASE 0xC7
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#define W25Q128FV_INSTRUCTION_ENTER_QPI_MODE 0x38
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#define W25Q128FV_INSTRUCTION_FAST_READ 0x0B
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#define W25Q128FV_INSTRUCTION_FAST_READ_QUAD_OUTPUT 0x6B
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#define W25Q128FV_INSTRUCTION_PAGE_PROGRAM 0x02
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#define W25Q128FV_INSTRUCTION_QUAD_PAGE_PROGRAM 0x32
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#define W25Q128FV_SR1_BIT_WRITE_IN_PROGRESS (1 << 0)
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#define W25Q128FV_SR1_BIT_WRITE_ENABLED (1 << 1)
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#define W25Q128FV_SR2_BIT_QUAD_ENABLE (1 << 1)
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//#define W25Q128FV_INSTRUCTION_WRITE_DISABLE 0x04
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//#define W25Q128FV_INSTRUCTION_PAGE_PROGRAM 0x02
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// Timings (2ms minimum to avoid 1 tick advance in consecutive calls to HAL_GetTick).
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#define W25Q128FV_TIMEOUT_PAGE_READ_MS 4
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#define W25Q128FV_TIMEOUT_RESET_MS 2 // tRST = 30us
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#define W25Q128FV_TIMEOUT_BLOCK_ERASE_64KB_MS 2000 // tBE2max = 2000ms, tBE2typ = 150ms
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#define W25Q128FV_TIMEOUT_CHIP_ERASE_MS (200 * 1000) // tCEmax 200s, tCEtyp = 40s
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#define W25Q128FV_TIMEOUT_PAGE_PROGRAM_MS 2 // tPPmax = 700us, tPPtyp = 250us
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#define W25Q128FV_TIMEOUT_WRITE_ENABLE_MS 2
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typedef enum {
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INITIAL_MODE_SPI = 0,
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INITIAL_MODE_QUADSPI,
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} w25q128fv_initialMode_e;
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typedef struct w25q128fvState_s {
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w25q128fv_initialMode_e initialMode;
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uint32_t currentWriteAddress;
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} w25q128fvState_t;
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w25q128fvState_t w25q128fvState = { 0 };
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static bool w25q128fv_waitForReady(flashDevice_t *fdevice);
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static void w25q128fv_waitForTimeout(flashDevice_t *fdevice);
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static void w25q128fv_setTimeout(flashDevice_t *fdevice, uint32_t timeoutMillis)
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{
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uint32_t now = HAL_GetTick();
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fdevice->timeoutAt = now + timeoutMillis;
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}
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static void w25q128fv_performOneByteCommand(flashDeviceIO_t *io, uint8_t command)
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{
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QUADSPI_TypeDef *quadSpi = io->handle.quadSpi;
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quadSpiTransmit1LINE(quadSpi, command, 0, NULL, 0);
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}
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static void w25q128fv_performCommandWithAddress(flashDeviceIO_t *io, uint8_t command, uint32_t address)
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{
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QUADSPI_TypeDef *quadSpi = io->handle.quadSpi;
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quadSpiInstructionWithAddress1LINE(quadSpi, command, 0, address & 0xffffff, W25Q128FV_ADDRESS_BITS);
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}
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static void w25q128fv_writeEnable(flashDevice_t *fdevice)
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{
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w25q128fv_performOneByteCommand(&fdevice->io, W25Q128FV_INSTRUCTION_WRITE_ENABLE);
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}
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static uint8_t w25q128fv_readRegister(flashDeviceIO_t *io, uint8_t command)
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{
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QUADSPI_TypeDef *quadSpi = io->handle.quadSpi;
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uint8_t in[1];
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quadSpiReceive1LINE(quadSpi, command, 0, in, W25Q128FV_STATUS_REGISTER_BITS / 8);
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return in[0];
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}
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static void w25q128fv_writeRegister(flashDeviceIO_t *io, uint8_t command, uint8_t data)
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{
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QUADSPI_TypeDef *quadSpi = io->handle.quadSpi;
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quadSpiTransmit1LINE(quadSpi, command, 0, &data, W25Q128FV_STATUS_REGISTER_BITS / 8);
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}
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static void w25q128fv_deviceReset(flashDevice_t *fdevice)
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{
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flashDeviceIO_t *io = &fdevice->io;
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w25q128fv_waitForReady(fdevice);
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w25q128fv_performOneByteCommand(io, W25Q128FV_INSTRUCTION_ENABLE_RESET);
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w25q128fv_performOneByteCommand(io, W25Q128FV_INSTRUCTION_RESET_DEVICE);
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w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_RESET_MS);
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w25q128fv_waitForTimeout(fdevice);
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w25q128fv_waitForReady(fdevice);
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#ifdef DISABLE_NONVOLATILE_QE_MODE // Use this if you encounter a chip with it's QE bit enabled when it shouldn't be.
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w25q128fv_performOneByteCommand(io, W25Q128FV_INSTRUCTION_WRITE_ENABLE);
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w25q128fv_writeRegister(io, W25Q128FV_INSTRUCTION_WRITE_STATUS2_REG, 0x00);
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#endif
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#if defined(USE_FLASH_WRITES_USING_4LINES) || defined(USE_FLASH_READS_USING_4LINES)
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uint8_t registerValue = w25q128fv_readRegister(io, W25Q128FV_INSTRUCTION_READ_STATUS2_REG);
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//
|
||||
// WARNING: DO NOT ENABLE QE bit if IO2/IO3 are connected to GND or VCC.
|
||||
//
|
||||
// See datasheet https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
|
||||
// W25Q128FV - Revision M - 7.1.10 Quad Enable
|
||||
//
|
||||
// There is no such warning for the W25Q128JV in the same documentation section
|
||||
// See datasheet https://www.winbond.com/resource-files/w25q128jv%20revg%2004082019%20plus.pdf
|
||||
// W25Q128JV - Revision G - 7.1.4 Quad Enable
|
||||
//
|
||||
|
||||
if ((registerValue & W25Q128FV_SR2_BIT_QUAD_ENABLE) == 0) {
|
||||
// Enable QUADSPI mode.
|
||||
registerValue = w25q128fv_readRegister(io, W25Q128FV_INSTRUCTION_READ_STATUS2_REG);
|
||||
|
||||
uint8_t newValue = registerValue;
|
||||
newValue |= W25Q128FV_SR2_BIT_QUAD_ENABLE;
|
||||
|
||||
//w25q128fv_performOneByteCommand(io, W25Q128FV_INSTRUCTION_WRITE_ENABLE);
|
||||
w25q128fv_performOneByteCommand(io, W25Q128FV_INSTRUCTION_VOLATILE_WRITE_ENABLE);
|
||||
w25q128fv_writeRegister(io, W25Q128FV_INSTRUCTION_WRITE_STATUS2_REG, newValue);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
bool w25q128fv_isReady(flashDevice_t *fdevice)
|
||||
{
|
||||
uint8_t status = w25q128fv_readRegister(&fdevice->io, W25Q128FV_INSTRUCTION_READ_STATUS1_REG);
|
||||
|
||||
bool busy = (status & W25Q128FV_SR1_BIT_WRITE_IN_PROGRESS);
|
||||
|
||||
return !busy;
|
||||
}
|
||||
|
||||
static bool w25q128fv_isWritable(flashDevice_t *fdevice)
|
||||
{
|
||||
uint8_t status = w25q128fv_readRegister(&fdevice->io, W25Q128FV_INSTRUCTION_READ_STATUS1_REG);
|
||||
|
||||
bool writable = (status & W25Q128FV_SR1_BIT_WRITE_ENABLED);
|
||||
|
||||
return writable;
|
||||
}
|
||||
|
||||
bool w25q128fv_hasTimedOut(flashDevice_t *fdevice)
|
||||
{
|
||||
uint32_t now = HAL_GetTick();
|
||||
if (cmp32(now, fdevice->timeoutAt) >= 0) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void w25q128fv_waitForTimeout(flashDevice_t *fdevice)
|
||||
{
|
||||
while (!w25q128fv_hasTimedOut(fdevice)) { }
|
||||
|
||||
fdevice->timeoutAt = 0;
|
||||
}
|
||||
|
||||
bool w25q128fv_waitForReady(flashDevice_t *fdevice)
|
||||
{
|
||||
bool ready = true;
|
||||
while (!w25q128fv_isReady(fdevice)) {
|
||||
if (w25q128fv_hasTimedOut(fdevice)) {
|
||||
ready = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
fdevice->timeoutAt = 0;
|
||||
|
||||
return ready;
|
||||
}
|
||||
|
||||
const flashVTable_t w25q128fv_vTable;
|
||||
|
||||
static void w25q128fv_deviceInit(flashDevice_t *flashdev);
|
||||
|
||||
bool w25q128fv_detect(flashDevice_t *fdevice, uint32_t chipID)
|
||||
{
|
||||
switch (chipID) {
|
||||
case JEDEC_ID_WINBOND_W25Q128FV_SPI:
|
||||
case JEDEC_ID_WINBOND_W25Q128FV_QUADSPI:
|
||||
case JEDEC_ID_WINBOND_W25Q128JV_QUADSPI:
|
||||
fdevice->geometry.sectors = 256;
|
||||
fdevice->geometry.pagesPerSector = 256;
|
||||
fdevice->geometry.pageSize = 256;
|
||||
break;
|
||||
|
||||
default:
|
||||
// Unsupported chip
|
||||
fdevice->geometry.sectors = 0;
|
||||
fdevice->geometry.pagesPerSector = 0;
|
||||
fdevice->geometry.sectorSize = 0;
|
||||
fdevice->geometry.totalSize = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
// use the chip id to determine the initial interface mode on cold-boot.
|
||||
switch (chipID) {
|
||||
case JEDEC_ID_WINBOND_W25Q128FV_SPI:
|
||||
w25q128fvState.initialMode = INITIAL_MODE_SPI;
|
||||
break;
|
||||
|
||||
case JEDEC_ID_WINBOND_W25Q128JV_QUADSPI:
|
||||
case JEDEC_ID_WINBOND_W25Q128FV_QUADSPI:
|
||||
w25q128fvState.initialMode = INITIAL_MODE_QUADSPI;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
fdevice->geometry.flashType = FLASH_TYPE_NOR;
|
||||
fdevice->geometry.sectorSize = fdevice->geometry.pagesPerSector * fdevice->geometry.pageSize;
|
||||
fdevice->geometry.totalSize = fdevice->geometry.sectorSize * fdevice->geometry.sectors;
|
||||
|
||||
w25q128fv_deviceReset(fdevice);
|
||||
|
||||
w25q128fv_deviceInit(fdevice);
|
||||
|
||||
fdevice->vTable = &w25q128fv_vTable;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void w25q128fv_eraseSector(flashDevice_t *fdevice, uint32_t address)
|
||||
{
|
||||
|
||||
w25q128fv_waitForReady(fdevice);
|
||||
|
||||
w25q128fv_writeEnable(fdevice);
|
||||
|
||||
w25q128fv_performCommandWithAddress(&fdevice->io, W25Q128FV_INSTRUCTION_BLOCK_ERASE_64KB, address);
|
||||
|
||||
w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_BLOCK_ERASE_64KB_MS);
|
||||
}
|
||||
|
||||
void w25q128fv_eraseCompletely(flashDevice_t *fdevice)
|
||||
{
|
||||
w25q128fv_waitForReady(fdevice);
|
||||
|
||||
w25q128fv_writeEnable(fdevice);
|
||||
|
||||
w25q128fv_performOneByteCommand(&fdevice->io, W25Q128FV_INSTRUCTION_CHIP_ERASE);
|
||||
|
||||
w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_CHIP_ERASE_MS);
|
||||
}
|
||||
|
||||
|
||||
static void w25q128fv_loadProgramData(flashDevice_t *fdevice, const uint8_t *data, int length)
|
||||
{
|
||||
w25q128fv_waitForReady(fdevice);
|
||||
|
||||
QUADSPI_TypeDef *quadSpi = fdevice->io.handle.quadSpi;
|
||||
|
||||
#ifdef USE_FLASH_WRITES_USING_4LINES
|
||||
quadSpiTransmitWithAddress4LINES(quadSpi, W25Q128FV_INSTRUCTION_QUAD_PAGE_PROGRAM, 0, w25q128fvState.currentWriteAddress, W25Q128FV_ADDRESS_BITS, data, length);
|
||||
#else
|
||||
quadSpiTransmitWithAddress1LINE(quadSpi, W25Q128FV_INSTRUCTION_PAGE_PROGRAM, 0, w25q128fvState.currentWriteAddress, W25Q128FV_ADDRESS_BITS, data, length);
|
||||
#endif
|
||||
|
||||
w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_PAGE_PROGRAM_MS);
|
||||
|
||||
w25q128fvState.currentWriteAddress += length;
|
||||
}
|
||||
|
||||
void w25q128fv_pageProgramBegin(flashDevice_t *fdevice, uint32_t address)
|
||||
{
|
||||
UNUSED(fdevice);
|
||||
w25q128fvState.currentWriteAddress = address;
|
||||
}
|
||||
|
||||
void w25q128fv_pageProgramContinue(flashDevice_t *fdevice, const uint8_t *data, int length)
|
||||
{
|
||||
w25q128fv_waitForReady(fdevice);
|
||||
|
||||
w25q128fv_writeEnable(fdevice);
|
||||
|
||||
// verify write enable is set.
|
||||
w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_WRITE_ENABLE_MS);
|
||||
bool writable = false;
|
||||
do {
|
||||
writable = w25q128fv_isWritable(fdevice);
|
||||
} while (!writable && w25q128fv_hasTimedOut(fdevice));
|
||||
|
||||
if (!writable) {
|
||||
return; // TODO report failure somehow.
|
||||
}
|
||||
|
||||
w25q128fv_loadProgramData(fdevice, data, length);
|
||||
|
||||
}
|
||||
|
||||
void w25q128fv_pageProgramFinish(flashDevice_t *fdevice)
|
||||
{
|
||||
UNUSED(fdevice);
|
||||
}
|
||||
|
||||
void w25q128fv_pageProgram(flashDevice_t *fdevice, uint32_t address, const uint8_t *data, int length)
|
||||
{
|
||||
w25q128fv_pageProgramBegin(fdevice, address);
|
||||
w25q128fv_pageProgramContinue(fdevice, data, length);
|
||||
w25q128fv_pageProgramFinish(fdevice);
|
||||
}
|
||||
|
||||
void w25q128fv_flush(flashDevice_t *fdevice)
|
||||
{
|
||||
UNUSED(fdevice);
|
||||
}
|
||||
|
||||
int w25q128fv_readBytes(flashDevice_t *fdevice, uint32_t address, uint8_t *buffer, int length)
|
||||
{
|
||||
if (!w25q128fv_waitForReady(fdevice)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
QUADSPI_TypeDef *quadSpi = fdevice->io.handle.quadSpi;
|
||||
#ifdef USE_FLASH_READS_USING_4LINES
|
||||
bool status = quadSpiReceiveWithAddress4LINES(quadSpi, W25Q128FV_INSTRUCTION_FAST_READ_QUAD_OUTPUT, 8, address, W25Q128FV_ADDRESS_BITS, buffer, length);
|
||||
#else
|
||||
bool status = quadSpiReceiveWithAddress1LINE(quadSpi, W25Q128FV_INSTRUCTION_FAST_READ, 8, address, W25Q128FV_ADDRESS_BITS, buffer, length);
|
||||
#endif
|
||||
w25q128fv_setTimeout(fdevice, W25Q128FV_TIMEOUT_PAGE_READ_MS);
|
||||
|
||||
if (!status) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
|
||||
|
||||
const flashGeometry_t* w25q128fv_getGeometry(flashDevice_t *fdevice)
|
||||
{
|
||||
return &fdevice->geometry;
|
||||
}
|
||||
|
||||
const flashVTable_t w25q128fv_vTable = {
|
||||
.isReady = w25q128fv_isReady,
|
||||
.waitForReady = w25q128fv_waitForReady,
|
||||
.eraseSector = w25q128fv_eraseSector,
|
||||
.eraseCompletely = w25q128fv_eraseCompletely,
|
||||
.pageProgramBegin = w25q128fv_pageProgramBegin,
|
||||
.pageProgramContinue = w25q128fv_pageProgramContinue,
|
||||
.pageProgramFinish = w25q128fv_pageProgramFinish,
|
||||
.pageProgram = w25q128fv_pageProgram,
|
||||
.flush = w25q128fv_flush,
|
||||
.readBytes = w25q128fv_readBytes,
|
||||
.getGeometry = w25q128fv_getGeometry,
|
||||
};
|
||||
|
||||
static void w25q128fv_deviceInit(flashDevice_t *flashdev)
|
||||
{
|
||||
UNUSED(flashdev);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#ifdef USE_FLASH_W25Q128FV
|
||||
|
||||
bool w25q128fv_detect(flashDevice_t *fdevice, uint32_t chipID);
|
||||
#endif
|
||||
|
|
@ -121,7 +121,7 @@
|
|||
#define SPI6_MISO_PIN NONE
|
||||
#define SPI6_MOSI_PIN NONE
|
||||
|
||||
// #define USE_QUADSPI
|
||||
#define USE_QUADSPI
|
||||
#define USE_QUADSPI_DEVICE_1
|
||||
|
||||
#define QUADSPI1_SCK_PIN NONE // PB2
|
||||
|
|
@ -224,6 +224,8 @@
|
|||
#define USE_FLASH_CHIP
|
||||
#define USE_FLASH_M25P16
|
||||
#define USE_FLASH_W25M
|
||||
#define USE_FLASH_W25Q128FV
|
||||
#define USE_FLASH_W25N01G
|
||||
#define FLASH_SPI_INSTANCE NULL
|
||||
#define FLASH_CS_PIN NONE
|
||||
#define USE_FLASHFS
|
||||
|
|
|
|||
Loading…
Reference in New Issue