From d924e59c3cd2c11b8850d504516b7078c638d40b Mon Sep 17 00:00:00 2001 From: jflyper Date: Mon, 24 Jun 2019 21:24:21 +0900 Subject: [PATCH] [H7][LIB][SDMMC] Workaround for SDMMC Errata 2.11.4 Application of STM32H750 - Apply workaround to the SDMMC Errata 2.11.4 (8446832) to V1.4.0 --- .../STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c | 11 +++++++++++ make/mcu/STM32H7.mk | 1 - 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c index ddbb5a3e0..0ab608fe3 100755 --- a/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c +++ b/lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c @@ -448,6 +448,17 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data->TransferMode |\ Data->DPSM); + // DC - See errata 2.11.4 - 8 SDMMC clock cycles must elapse before DTEN can be set. + // 32U below is used as a VERY rough guess that the SDMMC clock is 1/4 of the sytem clock, 8 * 4 = 32 and that the + // assembly below only takes 1 CPU cycle to run. All of which will be wrong, but right enough most of the time, especially + // when considering other processing overheads. + register uint32_t count = 32U; + do + { + count--; + } while(count > 0); + // DC - See errata 2.11.4 + /* Write to SDMMC DCTRL */ MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); diff --git a/make/mcu/STM32H7.mk b/make/mcu/STM32H7.mk index d14863770..e927bd7fb 100644 --- a/make/mcu/STM32H7.mk +++ b/make/mcu/STM32H7.mk @@ -86,7 +86,6 @@ EXCLUDES = \ stm32h7xx_ll_rcc.c \ stm32h7xx_ll_rng.c \ stm32h7xx_ll_rtc.c \ - stm32h7xx_ll_sdmmc.c \ stm32h7xx_ll_spi.c \ stm32h7xx_ll_swpmi.c \ stm32h7xx_ll_tim.c \