392 lines
8.9 KiB
C
392 lines
8.9 KiB
C
/*
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* This file is part of Cleanflight.
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*
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* Cleanflight is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Cleanflight is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "platform.h"
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#include "drivers/io.h"
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#include "drivers/io_impl.h"
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#include "drivers/rcc.h"
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#include "common/utils.h"
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// io ports defs are stored in array by index now
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struct ioPortDef_s {
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rccPeriphTag_t rcc;
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};
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#if defined(STM32F1)
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const struct ioPortDef_s ioPortDefs[] = {
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{ RCC_APB2(IOPA) },
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{ RCC_APB2(IOPB) },
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{ RCC_APB2(IOPC) },
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{ RCC_APB2(IOPD) },
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{ RCC_APB2(IOPE) },
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{
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#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_HD_VL)
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RCC_APB2(IOPF),
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#else
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0,
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#endif
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},
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{
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#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_HD_VL)
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RCC_APB2(IOPG),
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#else
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0,
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#endif
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},
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};
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#elif defined(STM32F3)
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const struct ioPortDef_s ioPortDefs[] = {
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{ RCC_AHB(GPIOA) },
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{ RCC_AHB(GPIOB) },
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{ RCC_AHB(GPIOC) },
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{ RCC_AHB(GPIOD) },
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{ RCC_AHB(GPIOE) },
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{ RCC_AHB(GPIOF) },
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};
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#elif defined(STM32F4)
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const struct ioPortDef_s ioPortDefs[] = {
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{ RCC_AHB1(GPIOA) },
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{ RCC_AHB1(GPIOB) },
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{ RCC_AHB1(GPIOC) },
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{ RCC_AHB1(GPIOD) },
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{ RCC_AHB1(GPIOE) },
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{ RCC_AHB1(GPIOF) },
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};
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#elif defined(STM32F7)
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const struct ioPortDef_s ioPortDefs[] = {
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{ RCC_AHB1(GPIOA) },
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{ RCC_AHB1(GPIOB) },
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{ RCC_AHB1(GPIOC) },
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{ RCC_AHB1(GPIOD) },
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{ RCC_AHB1(GPIOE) },
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{ RCC_AHB1(GPIOF) },
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};
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#endif
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ioRec_t* IO_Rec(IO_t io)
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{
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return io;
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}
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GPIO_TypeDef* IO_GPIO(IO_t io)
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{
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ioRec_t *ioRec = IO_Rec(io);
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return ioRec->gpio;
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}
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uint16_t IO_Pin(IO_t io)
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{
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ioRec_t *ioRec = IO_Rec(io);
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return ioRec->pin;
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}
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// port index, GPIOA == 0
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int IO_GPIOPortIdx(IO_t io)
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{
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if (!io)
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return -1;
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return (((size_t)IO_GPIO(io) - GPIOA_BASE) >> 10); // ports are 0x400 apart
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}
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int IO_EXTI_PortSourceGPIO(IO_t io)
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{
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return IO_GPIOPortIdx(io);
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}
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int IO_GPIO_PortSource(IO_t io)
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{
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return IO_GPIOPortIdx(io);
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}
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// zero based pin index
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int IO_GPIOPinIdx(IO_t io)
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{
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if (!io)
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return -1;
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return 31 - __builtin_clz(IO_Pin(io)); // CLZ is a bit faster than FFS
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}
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int IO_EXTI_PinSource(IO_t io)
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{
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return IO_GPIOPinIdx(io);
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}
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int IO_GPIO_PinSource(IO_t io)
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{
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return IO_GPIOPinIdx(io);
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}
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// mask on stm32f103, bit index on stm32f303
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uint32_t IO_EXTI_Line(IO_t io)
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{
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if (!io)
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return 0;
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#if defined(STM32F1)
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return 1 << IO_GPIOPinIdx(io);
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#elif defined(STM32F3)
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return IO_GPIOPinIdx(io);
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#elif defined(STM32F4)
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return 1 << IO_GPIOPinIdx(io);
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#elif defined(STM32F7)
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return 1 << IO_GPIOPinIdx(io);
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#elif defined(SIMULATOR_BUILD)
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return 1;
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#else
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# error "Unknown target type"
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#endif
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}
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bool IORead(IO_t io)
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{
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if (!io)
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return false;
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#if defined(USE_HAL_DRIVER)
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return !! HAL_GPIO_ReadPin(IO_GPIO(io),IO_Pin(io));
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#else
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return !! (IO_GPIO(io)->IDR & IO_Pin(io));
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#endif
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}
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void IOWrite(IO_t io, bool hi)
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{
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if (!io)
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return;
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#if defined(USE_HAL_DRIVER)
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if (hi) {
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HAL_GPIO_WritePin(IO_GPIO(io),IO_Pin(io),GPIO_PIN_SET);
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}
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else {
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HAL_GPIO_WritePin(IO_GPIO(io),IO_Pin(io),GPIO_PIN_RESET);
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}
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#elif defined(STM32F4)
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if (hi) {
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IO_GPIO(io)->BSRRL = IO_Pin(io);
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}
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else {
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IO_GPIO(io)->BSRRH = IO_Pin(io);
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}
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#else
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IO_GPIO(io)->BSRR = IO_Pin(io) << (hi ? 0 : 16);
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#endif
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}
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void IOHi(IO_t io)
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{
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if (!io)
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return;
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#if defined(USE_HAL_DRIVER)
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HAL_GPIO_WritePin(IO_GPIO(io),IO_Pin(io),GPIO_PIN_SET);
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#elif defined(STM32F4)
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IO_GPIO(io)->BSRRL = IO_Pin(io);
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#else
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IO_GPIO(io)->BSRR = IO_Pin(io);
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#endif
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}
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void IOLo(IO_t io)
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{
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if (!io)
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return;
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#if defined(USE_HAL_DRIVER)
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HAL_GPIO_WritePin(IO_GPIO(io),IO_Pin(io),GPIO_PIN_RESET);
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#elif defined(STM32F4)
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IO_GPIO(io)->BSRRH = IO_Pin(io);
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#else
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IO_GPIO(io)->BRR = IO_Pin(io);
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#endif
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}
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void IOToggle(IO_t io)
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{
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if (!io)
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return;
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uint32_t mask = IO_Pin(io);
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// Read pin state from ODR but write to BSRR because it only changes the pins
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// high in the mask value rather than all pins. XORing ODR directly risks
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// setting other pins incorrectly because it change all pins' state.
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#if defined(USE_HAL_DRIVER)
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(void)mask;
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HAL_GPIO_TogglePin(IO_GPIO(io),IO_Pin(io));
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#elif defined(STM32F4)
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if (IO_GPIO(io)->ODR & mask) {
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IO_GPIO(io)->BSRRH = mask;
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} else {
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IO_GPIO(io)->BSRRL = mask;
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}
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#else
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if (IO_GPIO(io)->ODR & mask)
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mask <<= 16; // bit is set, shift mask to reset half
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IO_GPIO(io)->BSRR = mask;
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#endif
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}
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// claim IO pin, set owner and resources
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void IOInit(IO_t io, resourceOwner_e owner, uint8_t index)
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{
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if (!io)
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return;
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ioRec_t *ioRec = IO_Rec(io);
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ioRec->owner = owner;
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ioRec->index = index;
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}
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void IORelease(IO_t io)
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{
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if (!io)
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return;
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ioRec_t *ioRec = IO_Rec(io);
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ioRec->owner = OWNER_FREE;
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}
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resourceOwner_e IOGetOwner(IO_t io)
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{
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if (!io)
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return OWNER_FREE;
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ioRec_t *ioRec = IO_Rec(io);
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return ioRec->owner;
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}
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#if defined(STM32F1)
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void IOConfigGPIO(IO_t io, ioConfig_t cfg)
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{
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if (!io)
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return;
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rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc;
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RCC_ClockCmd(rcc, ENABLE);
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GPIO_InitTypeDef init = {
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.GPIO_Pin = IO_Pin(io),
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.GPIO_Speed = cfg & 0x03,
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.GPIO_Mode = cfg & 0x7c,
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};
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GPIO_Init(IO_GPIO(io), &init);
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}
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#elif defined(STM32F7)
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void IOConfigGPIO(IO_t io, ioConfig_t cfg)
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{
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if (!io)
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return;
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rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc;
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RCC_ClockCmd(rcc, ENABLE);
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GPIO_InitTypeDef init = {
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.Pin = IO_Pin(io),
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.Mode = (cfg >> 0) & 0x13,
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.Speed = (cfg >> 2) & 0x03,
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.Pull = (cfg >> 5) & 0x03,
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};
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HAL_GPIO_Init(IO_GPIO(io), &init);
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}
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void IOConfigGPIOAF(IO_t io, ioConfig_t cfg, uint8_t af)
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{
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if (!io)
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return;
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rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc;
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RCC_ClockCmd(rcc, ENABLE);
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GPIO_InitTypeDef init = {
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.Pin = IO_Pin(io),
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.Mode = (cfg >> 0) & 0x13,
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.Speed = (cfg >> 2) & 0x03,
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.Pull = (cfg >> 5) & 0x03,
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.Alternate = af
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};
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HAL_GPIO_Init(IO_GPIO(io), &init);
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}
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#elif defined(STM32F3) || defined(STM32F4)
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void IOConfigGPIO(IO_t io, ioConfig_t cfg)
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{
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if (!io)
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return;
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rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc;
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RCC_ClockCmd(rcc, ENABLE);
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GPIO_InitTypeDef init = {
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.GPIO_Pin = IO_Pin(io),
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.GPIO_Mode = (cfg >> 0) & 0x03,
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.GPIO_Speed = (cfg >> 2) & 0x03,
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.GPIO_OType = (cfg >> 4) & 0x01,
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.GPIO_PuPd = (cfg >> 5) & 0x03,
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};
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GPIO_Init(IO_GPIO(io), &init);
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}
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void IOConfigGPIOAF(IO_t io, ioConfig_t cfg, uint8_t af)
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{
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if (!io)
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return;
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rccPeriphTag_t rcc = ioPortDefs[IO_GPIOPortIdx(io)].rcc;
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RCC_ClockCmd(rcc, ENABLE);
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GPIO_PinAFConfig(IO_GPIO(io), IO_GPIO_PinSource(io), af);
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GPIO_InitTypeDef init = {
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.GPIO_Pin = IO_Pin(io),
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.GPIO_Mode = (cfg >> 0) & 0x03,
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.GPIO_Speed = (cfg >> 2) & 0x03,
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.GPIO_OType = (cfg >> 4) & 0x01,
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.GPIO_PuPd = (cfg >> 5) & 0x03,
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};
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GPIO_Init(IO_GPIO(io), &init);
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}
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#endif
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static const uint16_t ioDefUsedMask[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_USED_LIST };
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static const uint8_t ioDefUsedOffset[DEFIO_PORT_USED_COUNT] = { DEFIO_PORT_OFFSET_LIST };
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ioRec_t ioRecs[DEFIO_IO_USED_COUNT];
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// initialize all ioRec_t structures from ROM
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// currently only bitmask is used, this may change in future
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void IOInitGlobal(void) {
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ioRec_t *ioRec = ioRecs;
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for (unsigned port = 0; port < ARRAYLEN(ioDefUsedMask); port++) {
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for (unsigned pin = 0; pin < sizeof(ioDefUsedMask[0]) * 8; pin++) {
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if (ioDefUsedMask[port] & (1 << pin)) {
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ioRec->gpio = (GPIO_TypeDef *)(GPIOA_BASE + (port << 10)); // ports are 0x400 apart
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ioRec->pin = 1 << pin;
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ioRec++;
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}
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}
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}
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}
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IO_t IOGetByTag(ioTag_t tag)
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{
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int portIdx = DEFIO_TAG_GPIOID(tag);
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int pinIdx = DEFIO_TAG_PIN(tag);
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if (portIdx >= DEFIO_PORT_USED_COUNT)
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return NULL;
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// check if pin exists
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if (!(ioDefUsedMask[portIdx] & (1 << pinIdx)))
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return NULL;
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// count bits before this pin on single port
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int offset = __builtin_popcount(((1 << pinIdx) - 1) & ioDefUsedMask[portIdx]);
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// and add port offset
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offset += ioDefUsedOffset[portIdx];
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return ioRecs + offset;
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}
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