145 lines
4.4 KiB
Plaintext
145 lines
4.4 KiB
Plaintext
/*
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*****************************************************************************
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**
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** File : stm32_flash_h750_exst.ld
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**
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** Abstract : Linker script for STM32H750xB Device with
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** 512K AXI-RAM mapped onto AXI bus on D1 domain
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** 128K SRAM1 mapped on D2 domain
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** 128K SRAM2 mapped on D2 domain
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** 32K SRAM3 mapped on D2 domain
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** 64K SRAM4 mapped on D3 domain
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** 64K ITCM
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** 128K DTCM
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/*
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0x00000000 to 0x0000FFFF 64K ITCM
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0x20000000 to 0x2001FFFF 128K DTCM, main RAM
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0x24000000 to 0x2407FFFF 512K AXI SRAM, D1 domain
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0x30000000 to 0x3001FFFF 128K SRAM1, D2 domain
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0x30020000 to 0x3003FFFF 128K SRAM2, D2 domain
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0x30040000 to 0x30047FFF 32K SRAM3, D2 domain, unused
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0x38000000 to 0x3800FFFF 64K SRAM4, D3 domain, unused
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0x38800000 to 0x38800FFF 4K BACKUP SRAM, Backup domain, unused
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0x08000000 to 0x0801FFFF 128K isr vector, startup code, firmware, no config! // FLASH_Sector_0
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*/
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/*
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For H7 EXST (External Storage) targets a binary is built that is placed on an external device.
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The bootloader will then copy this entire binary to RAM, at the CODE_RAM address. The bootloader
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then executes code at the CODE_RAM address. The address of CODE_RAM is fixed to 0x24010000
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and must not be changed.
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Currently, this is inefficient as there are two copies of some sections in RAM. e.g. .tcm_code.
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It would be technically possible to free more RAM by having a more intelligent build system
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and bootloader which creates files for each of the sections that are usually copied from flash
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to ram and one section for the main code. e.g. one file for .tcm_code, one file for .data and
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one for the main code/data, then load each to the appropriate address and adjust the usual startup
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code which will no-longer need to duplicate code/data sections from RAM to ITCM/DTCM RAM.
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The initial CODE_RAM is sized at 448K to enable all firmware features and to as much RAM free as
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possible.
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*/
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/* see .exst section below */
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_exst_hash_size = 64;
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/* Specify the memory areas */
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MEMORY
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{
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ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 64K
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CODE_RAM (rx) : ORIGIN = 0x24010000, LENGTH = 448K - _exst_hash_size /* hard coded start address, as required by SPRACINGH7 boot loader, don't change! */
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EXST_HASH (rx) : ORIGIN = 0x24010000 + LENGTH(CODE_RAM), LENGTH = _exst_hash_size
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D2_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 256K /* SRAM1 + SRAM2 */
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MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
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QUADSPI (rx) : ORIGIN = 0x90000000, LENGTH = 0K
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}
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REGION_ALIAS("STACKRAM", DTCM_RAM)
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REGION_ALIAS("FASTRAM", DTCM_RAM)
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REGION_ALIAS("MAIN", CODE_RAM)
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INCLUDE "stm32_h750_common.ld"
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SECTIONS
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{
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/* used during startup to initialized dmaram_data */
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_sdmaram_idata = LOADADDR(.dmaram_data);
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. = ALIGN(32);
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.dmaram_data :
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{
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PROVIDE(dmaram_start = .);
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_sdmaram = .;
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_dmaram_start__ = _sdmaram;
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_sdmaram_data = .; /* create a global symbol at data start */
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*(.dmaram_data) /* .data sections */
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*(.dmaram_data*) /* .data* sections */
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. = ALIGN(32);
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_edmaram_data = .; /* define a global symbol at data end */
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} >RAM AT >MAIN
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. = ALIGN(32);
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.dmaram_bss (NOLOAD) :
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{
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_sdmaram_bss = .;
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__dmaram_bss_start__ = _sdmaram_bss;
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*(.dmaram_bss)
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*(SORT_BY_ALIGNMENT(.dmaram_bss*))
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. = ALIGN(32);
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_edmaram_bss = .;
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__dmaram_bss_end__ = _edmaram_bss;
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} >RAM
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. = ALIGN(32);
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.DMA_RAM (NOLOAD) :
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{
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KEEP(*(.DMA_RAM))
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PROVIDE(dmaram_end = .);
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_edmaram = .;
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_dmaram_end__ = _edmaram;
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} >RAM
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.DMA_RW_D2 (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarw_start = .);
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_sdmarw = .;
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_dmarw_start__ = _sdmarw;
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KEEP(*(.DMA_RW))
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PROVIDE(dmarw_end = .);
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_edmarw = .;
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_dmarw_end__ = _edmarw;
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} >D2_RAM
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.DMA_RW_AXI (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE(dmarwaxi_start = .);
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_sdmarwaxi = .;
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_dmarwaxi_start__ = _sdmarwaxi;
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KEEP(*(.DMA_RW_AXI))
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PROVIDE(dmarwaxi_end = .);
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_edmarwaxi = .;
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_dmarwaxi_end__ = _edmarwaxi;
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} >RAM
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}
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INCLUDE "stm32_h750_common_post.ld"
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INCLUDE "stm32_ram_h750_exst_post.ld"
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