2014-09-14 17:39:58 -07:00
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/*
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2015-10-08 14:09:39 -07:00
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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This file is part of ChibiOS.
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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ChibiOS is free software; you can redistribute it and/or modify
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2014-09-14 17:39:58 -07:00
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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2015-10-08 14:09:39 -07:00
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ChibiOS is distributed in the hope that it will be useful,
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2014-09-14 17:39:58 -07:00
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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2015-10-08 14:09:39 -07:00
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* STM32F407xG memory setup.
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* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
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2019-04-15 13:48:34 -07:00
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* Note: flash2 length decreased by 8 bytes to use it as hardcoded CRC
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* flags.
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2014-09-14 17:39:58 -07:00
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*/
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MEMORY
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{
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flash : org = 0x08000000, len = 16k
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2022-01-18 11:31:24 -08:00
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flash2 : org = 0x0800C000, len = 524288 - 16 /* NEW_APP_MAX_SIZE - CRC_INFO */
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crcinfo : org = 0x0807FFF0, len = 8 /* CRC info */
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2015-10-08 14:09:39 -07:00
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ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
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ram1 : org = 0x20000000, len = 112k /* SRAM1 */
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ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
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ram3 : org = 0x00000000, len = 0
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2022-10-03 03:40:02 -07:00
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ram4 : org = 0x10000000, len = 62k /* CCM SRAM */
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libif : org = 0x1000F800, len = 2k
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2015-10-08 14:09:39 -07:00
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ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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2014-09-14 17:39:58 -07:00
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}
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2015-10-08 14:09:39 -07:00
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts*/
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REGION_ALIAS("MAIN_STACK_RAM", ram0);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram0);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram0);
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__ram0_start__ = ORIGIN(ram0);
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__ram0_size__ = LENGTH(ram0);
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__ram0_end__ = __ram0_start__ + __ram0_size__;
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__ram1_start__ = ORIGIN(ram1);
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__ram1_size__ = LENGTH(ram1);
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__ram1_end__ = __ram1_start__ + __ram1_size__;
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__ram2_start__ = ORIGIN(ram2);
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__ram2_size__ = LENGTH(ram2);
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__ram2_end__ = __ram2_start__ + __ram2_size__;
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__ram3_start__ = ORIGIN(ram3);
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__ram3_size__ = LENGTH(ram3);
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__ram3_end__ = __ram3_start__ + __ram3_size__;
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__ram4_start__ = ORIGIN(ram4);
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__ram4_size__ = LENGTH(ram4);
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__ram4_end__ = __ram4_start__ + __ram4_size__;
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__ram5_start__ = ORIGIN(ram5);
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__ram5_size__ = LENGTH(ram5);
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__ram5_end__ = __ram5_start__ + __ram5_size__;
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__ram6_start__ = ORIGIN(ram6);
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__ram6_size__ = LENGTH(ram6);
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__ram6_end__ = __ram6_start__ + __ram6_size__;
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__ram7_start__ = ORIGIN(ram7);
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__ram7_size__ = LENGTH(ram7);
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__ram7_end__ = __ram7_start__ + __ram7_size__;
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ENTRY(Reset_Handler)
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2014-09-14 17:39:58 -07:00
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SECTIONS
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{
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. = 0;
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_text = .;
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startup : ALIGN(16) SUBALIGN(16)
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{
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KEEP(*(.vectors))
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2014-09-14 17:39:58 -07:00
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} > flash
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constructors : ALIGN(4) SUBALIGN(4)
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{
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PROVIDE(__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE(__init_array_end = .);
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} > flash2
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destructors : ALIGN(4) SUBALIGN(4)
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{
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PROVIDE(__fini_array_start = .);
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KEEP(*(.fini_array))
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KEEP(*(SORT(.fini_array.*)))
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PROVIDE(__fini_array_end = .);
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} > flash2
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.text : ALIGN(16) SUBALIGN(16)
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{
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*(.text)
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*(.text.*)
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*(.rodata)
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*(.rodata.*)
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*(.glue_7t)
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*(.glue_7)
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*(.gcc*)
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} > flash2
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > flash2
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.ARM.exidx : {
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PROVIDE(__exidx_start = .);
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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PROVIDE(__exidx_end = .);
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} > flash2
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.eh_frame_hdr :
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{
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*(.eh_frame_hdr)
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} > flash2
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.eh_frame : ONLY_IF_RO
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{
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*(.eh_frame)
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} > flash2
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.textalign : ONLY_IF_RO
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{
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. = ALIGN(8);
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} > flash2
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2015-10-08 14:09:39 -07:00
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. = ALIGN(4);
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2014-09-14 17:39:58 -07:00
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_etext = .;
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_textdata = _etext;
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2019-04-17 17:27:43 -07:00
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2022-01-18 11:31:24 -08:00
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_crcinfo_start_address = 0x0807FFF0;
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2019-04-17 17:27:43 -07:00
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.crcinfo _crcinfo_start_address :
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{
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KEEP(*(.crcinfo))
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} > crcinfo
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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.mstack :
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{
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. = ALIGN(8);
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__main_stack_base__ = .;
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. += __main_stack_size__;
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. = ALIGN(8);
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__main_stack_end__ = .;
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2015-10-08 14:09:39 -07:00
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} > MAIN_STACK_RAM
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.pstack :
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{
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__process_stack_base__ = .;
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__main_thread_stack_base__ = .;
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. += __process_stack_size__;
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. = ALIGN(8);
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__process_stack_end__ = .;
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__main_thread_stack_end__ = .;
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2015-10-08 14:09:39 -07:00
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} > PROCESS_STACK_RAM
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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.data : ALIGN(4)
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2014-09-14 17:39:58 -07:00
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{
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. = ALIGN(4);
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PROVIDE(_data = .);
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*(.data)
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*(.data.*)
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*(.ramtext)
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. = ALIGN(4);
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PROVIDE(_edata = .);
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2015-10-08 14:09:39 -07:00
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} > DATA_RAM AT > flash2
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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.bss : ALIGN(4)
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{
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. = ALIGN(4);
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PROVIDE(_bss_start = .);
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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PROVIDE(_bss_end = .);
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PROVIDE(end = .);
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} > BSS_RAM
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.ram0 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram0)
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*(.ram0.*)
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. = ALIGN(4);
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__ram0_free__ = .;
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} > ram0
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.ram1 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram1)
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*(.ram1.*)
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. = ALIGN(4);
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__ram1_free__ = .;
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} > ram1
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.ram2 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram2)
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*(.ram2.*)
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. = ALIGN(4);
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__ram2_free__ = .;
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} > ram2
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.ram3 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram3)
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*(.ram3.*)
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. = ALIGN(4);
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__ram3_free__ = .;
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} > ram3
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.ram4 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram4)
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*(.ram4.*)
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. = ALIGN(4);
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__ram4_free__ = .;
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} > ram4
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2022-05-11 13:10:42 -07:00
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.libif (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.libif)
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} > libif
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2015-10-08 14:09:39 -07:00
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.ram5 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram5)
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*(.ram5.*)
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. = ALIGN(4);
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__ram5_free__ = .;
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} > ram5
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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.ram6 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram6)
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*(.ram6.*)
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. = ALIGN(4);
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__ram6_free__ = .;
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} > ram6
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.ram7 (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.ram7)
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*(.ram7.*)
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. = ALIGN(4);
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__ram7_free__ = .;
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} > ram7
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}
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2014-09-14 17:39:58 -07:00
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2015-10-08 14:09:39 -07:00
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/* Heap default boundaries, it is defaulted to be the non-used part
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of ram0 region.*/
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__heap_base__ = __ram0_free__;
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__heap_end__ = __ram0_end__;
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