2022-02-20 04:44:01 -08:00
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/*
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Copyright 2022 Benjamin Vedder benjamin@vedder.se
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This file is part of the VESC firmware.
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The VESC firmware is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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The VESC firmware is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "encoder_cfg.h"
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#include "hw.h"
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#include "ch.h"
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#include "hal.h"
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// Stack area for the running encoder
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static THD_WORKING_AREA(encoder_thread_wa, 512);
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#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) // 42 MHz 21 MHZ
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#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) // 21 MHz 10.5 MHz
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#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) // 10.5 MHz 5.25 MHz
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#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) // 5.25 MHz 2.626 MHz
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#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) // 2.626 MHz 1.3125 MHz
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#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) // 1.3125 MHz 656.25 KHz
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#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) // 656.25 KHz 328.125 KHz
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#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) // 328.125 KHz 164.06 KHz
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#define SPI_DATASIZE_16BIT SPI_CR1_DFF
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AS504x_config_t encoder_cfg_as504x = {
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{
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HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3,
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HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1,
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2022-02-28 05:30:48 -08:00
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#ifdef AS504x_MOSI_GPIO
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AS504x_MOSI_GPIO, AS504x_MOSI_PIN,
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2022-02-20 04:44:01 -08:00
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#else
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0, 0,
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#endif
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HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2,
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0, // has_started
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0, // has_error
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{{NULL, NULL}, NULL, NULL} // Mutex
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},
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{0} // State
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};
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AD2S1205_config_t encoder_cfg_ad2s1205 = {
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{ // BB_SPI
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HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3,
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HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1,
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#if defined(HW_SPI_PORT_MOSI) && AS504x_USE_SW_MOSI_PIN
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HW_SPI_PORT_MOSI, HW_SPI_PIN_MOSI,
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#else
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0, 0,
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#endif
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HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2,
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0, // has_started
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0, // has_error
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{{NULL, NULL}, NULL, NULL} // Mutex
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},
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{0},
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};
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MT6816_config_t encoder_cfg_mt6816 = {
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#ifdef HW_SPI_DEV
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&HW_SPI_DEV, // spi_dev
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{//HARDWARE SPI CONFIG
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NULL, HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, SPI_BaudRatePrescaler_4 |
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SPI_CR1_CPOL | SPI_CR1_CPHA | SPI_DATASIZE_16BIT
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},
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/*NSS*/HW_SPI_PORT_NSS, HW_SPI_PIN_NSS,
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/*SCK*/HW_SPI_PORT_SCK, HW_SPI_PIN_SCK,
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/*MOSI*/HW_SPI_PORT_MOSI, HW_SPI_PIN_MOSI,
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/*MISO*/HW_SPI_PORT_MISO, HW_SPI_PIN_MISO,
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{0, 0, 0, 0, 0, 0, 0},
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#else
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0,
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{0},
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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{0, 0, 0, 0, 0, 0, 0},
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#endif
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};
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2022-02-20 07:22:38 -08:00
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ABI_config_t encoder_cfg_ABI = {
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2022-02-20 04:44:01 -08:00
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10000, // counts
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HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1,
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HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2,
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2022-02-20 07:22:38 -08:00
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HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3,
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HW_ENC_TIM,
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HW_ENC_TIM_AF,
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HW_ENC_EXTI_PORTSRC,
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HW_ENC_EXTI_PINSRC,
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HW_ENC_EXTI_LINE,
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HW_ENC_EXTI_CH,
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{0, 0, 0}, // State
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2022-02-20 04:44:01 -08:00
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};
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ENCSINCOS_config_t encoder_cfg_sincos = {0};
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TS5700N8501_config_t encoder_cfg_TS5700N8501 = {
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#if defined(HW_ADC_EXT_GPIO) && defined(HW_ADC_EXT_GPIO)
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&HW_UART_DEV,
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2022-02-20 08:32:35 -08:00
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HW_UART_GPIO_AF,
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2022-02-20 04:44:01 -08:00
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/*UART PINOUT*/
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HW_UART_TX_PORT, HW_UART_TX_PIN,
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HW_UART_RX_PORT, HW_UART_RX_PIN,
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HW_ADC_EXT_GPIO, HW_ADC_EXT_PIN,
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{// UART CONFIG
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2500000,
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0,
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USART_CR2_LINEN,
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0
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},
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#else
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2022-02-20 08:32:35 -08:00
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0,
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2022-02-20 04:44:01 -08:00
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0,
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0, 0,
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0, 0,
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0, 0,
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{0},
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#endif
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encoder_thread_wa,
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sizeof(encoder_thread_wa),
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{0}
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};
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