rusefi
/
bldc
mirror of https://github.com/rusefi/bldc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #549 from TechAUmNu/add-hardware 

Support for latest TeamTriforceUK hardware
This commit is contained in:
Benjamin Vedder 2022-11-09 11:41:02 +01:00 committed by GitHub
parent 37e5a9cbc9 d4ffa77413
commit 1130747bc3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
21 changed files with 1828 additions and 216 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
datatypes.h
View File

@ -156,6 +156,7 @@ typedef enum {
FAULT_CODE_ENCODER_MAGNET_TOO_STRONG, FAULT_CODE_ENCODER_MAGNET_TOO_STRONG,
FAULT_CODE_PHASE_FILTER, FAULT_CODE_PHASE_FILTER,
FAULT_CODE_ENCODER_FAULT, FAULT_CODE_ENCODER_FAULT,
FAULT_CODE_LV_OUTPUT_FAULT,
} mc_fault_code; } mc_fault_code;
typedef enum { typedef enum {

3
hwconf/board.h
View File

@ -36,9 +36,12 @@
#define STM32_LSECLK 0U #define STM32_LSECLK 0U
#endif #endif
// Definition moved to mcuconf.h with the other clock settings
/*
#if !defined(STM32_HSECLK) #if !defined(STM32_HSECLK)
#define STM32_HSECLK 8000000U #define STM32_HSECLK 8000000U
#endif #endif
*/
/* /*
* Board voltages. * Board voltages.

121
hwconf/mcuconf.h
View File

@ -41,62 +41,73 @@
// Internal RC osc // Internal RC osc
#ifdef HW_USE_INTERNAL_RC #ifdef HW_USE_INTERNAL_RC
#define STM32_NO_INIT FALSE #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE #define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE #define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE #define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLM_VALUE 16 #define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 336 #define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2 #define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7 #define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8 #define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5 #define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE TRUE #define STM32_PVD_ENABLE TRUE
#define STM32_PLS STM32_PLS_LEV6 #define STM32_PLS STM32_PLS_LEV6
#define STM32_BKPRAM_ENABLE FALSE #define STM32_BKPRAM_ENABLE FALSE
#else #else
// 8M XTAL // 8M XTAL / 25MHz External
#define STM32_NO_INIT FALSE #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE #define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE #define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE #define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8 #ifdef HW_USE_25MHZ_EXT_CLOCK
#define STM32_PLLN_VALUE 336 #define STM32_PLLM_VALUE 25
#define STM32_PLLP_VALUE 2 #define STM32_HSE_BYPASS TRUE
#define STM32_PLLQ_VALUE 7 #if !defined(STM32_HSECLK)
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HSECLK 25000000U
#define STM32_PPRE1 STM32_PPRE1_DIV4 #endif
#define STM32_PPRE2 STM32_PPRE2_DIV2 #else
#define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_PLLM_VALUE 8
#define STM32_RTCPRE_VALUE 8 #if !defined(STM32_HSECLK)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_HSECLK 8000000U
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #endif
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #endif
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_PLLN_VALUE 336
#define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLP_VALUE 2
#define STM32_PLLI2SN_VALUE 192 #define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SR_VALUE 5 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PVD_ENABLE TRUE #define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PLS STM32_PLS_LEV6 #define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_BKPRAM_ENABLE FALSE #define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE TRUE
#define STM32_PLS STM32_PLS_LEV6
#define STM32_BKPRAM_ENABLE FALSE
#endif #endif
/* /*

0
hwconf/teamtriforceuk/a200s/hw_a200s_v2.1.h → hwconf/teamtriforceuk/a200s_v2/hw_a200s_v2.1.h
View File

0
hwconf/teamtriforceuk/a200s/hw_a200s_v2.2.h → hwconf/teamtriforceuk/a200s_v2/hw_a200s_v2.2.h
View File

2
hwconf/teamtriforceuk/a200s/hw_a200s_v2_core.c → hwconf/teamtriforceuk/a200s_v2/hw_a200s_v2_core.c
View File

@ -20,7 +20,7 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#include "stm32f4xx_conf.h" #include "stm32f4xx_conf.h"
#include "utils_math.h" #include "utils.h"
#include <math.h> #include <math.h>
#include "mc_interface.h" #include "mc_interface.h"

0
hwconf/teamtriforceuk/a200s/hw_a200s_v2_core.h → hwconf/teamtriforceuk/a200s_v2/hw_a200s_v2_core.h
View File

27
hwconf/teamtriforceuk/a200s_v3/hw_a200s_v3.h Normal file
View File

@ -0,0 +1,27 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This file is part of the VESC firmware.
The VESC firmware is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
The VESC firmware is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_A200S_V3_H_
#define HW_A200S_V3_H_
#define HW_A200S_V3
#include "hw_a200s_v3_core.h"
#endif /* HW_A200S_V3_H_ */

464
hwconf/teamtriforceuk/a200s_v3/hw_a200s_v3_core.c Normal file
View File

@ -0,0 +1,464 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "hw.h"
#include "ch.h"
#include "hal.h"
#include "stm32f4xx_conf.h"
#include "utils.h"
#include <math.h>
#include "mc_interface.h"
#include "commands.h"
#include "terminal.h"
#include "mcpwm.h"
#include "mcpwm_foc.h"
#include "gpdrive.h"
#include "app.h"
#include "mempools.h"
#include "timeout.h"
#include "stdio.h"
// Variables
static volatile bool i2c_running = false;
// Private functions
static void terminal_cmd_doublepulse(int argc, const char** argv);
// I2C configuration
static const I2CConfig i2cfg = {
OPMODE_I2C,
100000,
STD_DUTY_CYCLE
};
void hw_init_gpio(void) {
// GPIO clock enable
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
// LEDs
palSetPadMode(GPIOB, 5,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(GPIOB, 7,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
// GPIOA Configuration: Channel 1 to 3 as alternate function push-pull
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
// Hall sensors
palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, PAL_MODE_INPUT_PULLUP);
// Phase filters
palSetPadMode(GPIOC, 9, PAL_MODE_OUTPUT_OPENDRAIN);
palSetPadMode(GPIOC, 13, PAL_MODE_OUTPUT_OPENDRAIN);
palSetPadMode(GPIOC, 14, PAL_MODE_OUTPUT_OPENDRAIN);
PHASE_FILTER_OFF();
// Current filter
palSetPadMode(GPIOC, 15, PAL_MODE_OUTPUT_OPENDRAIN);
palSetPadMode(GPIOB, 1, PAL_MODE_OUTPUT_OPENDRAIN);
CURRENT_FILTER_OFF();
// AUX pin
AUX_OFF();
palSetPadMode(AUX_GPIO, AUX_PIN,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
// ADC Pins
palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOB, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOB, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 4, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 5, PAL_MODE_INPUT_ANALOG);
//register terminal callbacks
//double pulse not possible with dual motor setup
terminal_register_command_callback(
"double_pulse",
"Start a double pulse test",
0,
terminal_cmd_doublepulse);
}
void hw_setup_adc_channels(void) {
// ADC1 regular channels
ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 3, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 4, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC1, ADC_Channel_Vrefint, 5, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 6, ADC_SampleTime_15Cycles);
// ADC2 regular channels
ADC_RegularChannelConfig(ADC2, ADC_Channel_1, 1, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC2, ADC_Channel_6, 3, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC2, ADC_Channel_15, 4, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 5, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC2, ADC_Channel_9, 6, ADC_SampleTime_15Cycles);
// ADC3 regular channels
ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 1, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC3, ADC_Channel_3, 3, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC3, ADC_Channel_13, 4, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC3, ADC_Channel_1, 5, ADC_SampleTime_15Cycles);
ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 6, ADC_SampleTime_15Cycles);
// Injected channels
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 3, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 3, ADC_SampleTime_15Cycles);
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles);
}
void hw_start_i2c(void) {
i2cAcquireBus(&HW_I2C_DEV);
if (!i2c_running) {
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
i2cStart(&HW_I2C_DEV, &i2cfg);
i2c_running = true;
}
i2cReleaseBus(&HW_I2C_DEV);
}
void hw_stop_i2c(void) {
i2cAcquireBus(&HW_I2C_DEV);
if (i2c_running) {
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, PAL_MODE_INPUT);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, PAL_MODE_INPUT);
i2cStop(&HW_I2C_DEV);
i2c_running = false;
}
i2cReleaseBus(&HW_I2C_DEV);
}
/**
* Try to restore the i2c bus
*/
void hw_try_restore_i2c(void) {
if (i2c_running) {
i2cAcquireBus(&HW_I2C_DEV);
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
chThdSleep(1);
for(int i = 0;i < 16;i++) {
palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
}
// Generate start then stop condition
palClearPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
chThdSleep(1);
palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
HW_I2C_DEV.state = I2C_STOP;
i2cStart(&HW_I2C_DEV, &i2cfg);
i2cReleaseBus(&HW_I2C_DEV);
}
}
int inject_temp = 0;
float hw_a200s_get_temp_mos(void) {
float t_board = NTC_TEMP_MOS1();
UTILS_NAN_ZERO(t_board);
const float motor_current_now = fabs(mc_interface_get_tot_current_directional_filtered()); // To work out mosfet temperature
// iteration 1, find roughly
float mos_temp = t_board + ((SQ(motor_current_now) * HW_TEMP_MOSFET_R/HW_TEMP_MOSFET_COUNT)/HW_TEMP_NUM_PHASES * HW_TEMP_MOSFET_KW);
// iteration 2, use junction temperature to calaculate new RDSon
float mos_r_temp_comp = HW_TEMP_MOSFET_R * (0.0055f * mos_temp + 0.85f); // best fit on the graph, could use a polynomial
mos_temp = t_board + ((SQ(motor_current_now) * mos_r_temp_comp/HW_TEMP_MOSFET_COUNT)/HW_TEMP_NUM_PHASES * HW_TEMP_MOSFET_KW);
static float mos_temp_filtered = 0.0;
UTILS_LP_FAST(mos_temp_filtered, mos_temp, 0.0003);
return mos_temp_filtered;
}
float hw_a200s_get_temp_shunt(void) {
float t_board = NTC_TEMP_MOS1();
UTILS_NAN_ZERO(t_board);
const float input_current_now = fabs(mc_interface_get_tot_current_in_filtered()); // To work out shunt temperature
float shunt_temp = t_board +((((SQ(input_current_now) * CURRENT_SHUNT_RES)/HW_TEMP_NUM_PHASES)) * HW_TEMP_MOSFET_KW);
static float shunt_temp_filtered = 0.0;
UTILS_LP_FAST(shunt_temp_filtered, shunt_temp, 0.0003);
return shunt_temp_filtered;
}
float hw_a200s_get_temp(void) {
float t1 = hw_a200s_get_temp_mos();
float t2 = hw_a200s_get_temp_shunt();
float t_board = NTC_TEMP_MOS1();
float res;
if (t1 > t2) {
res = t1;
} else {
res = t2;
}
// If the board temp is still higher use that
if (res < t_board) {
res = t_board;
}
return res;
}
static void terminal_cmd_doublepulse(int argc, const char** argv)
{
(void)argc;
(void)argv;
int preface, pulse1, breaktime, pulse2;
int utick;
int deadtime = -1;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
if (argc < 5) {
commands_printf("Usage: double_pulse <preface> <pulse1> <break> <pulse2> [deadtime]");
commands_printf(" preface: idle time in us");
commands_printf(" pulse1: high time of pulse 1 in us");
commands_printf(" break: break between pulses in us");
commands_printf(" pulse2: high time of pulse 2 in us");
commands_printf(" deadtime: overwrite deadtime, in ns");
return;
}
sscanf(argv[1], "%d", &preface);
sscanf(argv[2], "%d", &pulse1);
sscanf(argv[3], "%d", &breaktime);
sscanf(argv[4], "%d", &pulse2);
if (argc == 6) {
sscanf(argv[5], "%d", &deadtime);
}
timeout_configure_IWDT_slowest();
utick = (int)(SYSTEM_CORE_CLOCK / 1000000);
mcpwm_deinit();
mcpwm_foc_deinit();
gpdrive_deinit();
TIM_Cmd(TIM1, DISABLE);
TIM_Cmd(TIM4, DISABLE);
//TIM4 als Trigger Timer
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
TIM_TimeBaseStructure.TIM_Period = (SYSTEM_CORE_CLOCK / 20000);
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
TIM_SelectMasterSlaveMode(TIM4, TIM_MasterSlaveMode_Enable);
TIM_SelectOutputTrigger(TIM4, TIM_TRGOSource_Enable);
TIM4->CNT = 0;
// TIM1
// TIM1 clock enable
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
// Time Base configuration
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = (preface + pulse1) * utick;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
// Channel 1, 2 and 3 Configuration in PWM mode
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_Pulse = preface * utick;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC2Init(TIM1, &TIM_OCInitStructure);
TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC3Init(TIM1, &TIM_OCInitStructure);
TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM2);
TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_Inactive);
TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_Inactive);
TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
TIM_GenerateEvent(TIM1, TIM_EventSource_COM);
// Automatic Output enable, Break, dead time and lock configuration
TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
if (deadtime < 0) {
TIM_BDTRInitStructure.TIM_DeadTime = conf_general_calculate_deadtime(HW_DEAD_TIME_NSEC, SYSTEM_CORE_CLOCK);
} else {
TIM_BDTRInitStructure.TIM_DeadTime = conf_general_calculate_deadtime(deadtime, SYSTEM_CORE_CLOCK);
}
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
TIM_CCPreloadControl(TIM1, ENABLE);
TIM_ARRPreloadConfig(TIM1, ENABLE);
TIM1->CNT = 0;
TIM1->EGR = TIM_EGR_UG;
TIM_SelectSlaveMode(TIM1, TIM_SlaveMode_Trigger);
TIM_SelectInputTrigger(TIM1, TIM_TS_ITR3);
TIM_SelectOnePulseMode(TIM1, TIM_OPMode_Single);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
TIM_Cmd(TIM1, ENABLE);
//Timer 4 triggert Timer 1
TIM_Cmd(TIM4, ENABLE);
TIM_Cmd(TIM4, DISABLE);
TIM1->ARR = (breaktime + pulse2) * utick;
TIM1->CCR1 = breaktime * utick;
while (TIM1->CNT != 0);
TIM_Cmd(TIM4, ENABLE);
chThdSleepMilliseconds(1);
TIM_CtrlPWMOutputs(TIM1, DISABLE);
mc_configuration* mcconf = mempools_alloc_mcconf();
*mcconf = *mc_interface_get_configuration();
switch (mcconf->motor_type) {
case MOTOR_TYPE_BLDC:
case MOTOR_TYPE_DC:
mcpwm_init(mcconf);
break;
case MOTOR_TYPE_FOC:
mcpwm_foc_init(mcconf, mcconf);
break;
case MOTOR_TYPE_GPD:
gpdrive_init(mcconf);
break;
default:
break;
}
commands_printf("Done");
return;
}

309
hwconf/teamtriforceuk/a200s_v3/hw_a200s_v3_core.h Normal file
View File

@ -0,0 +1,309 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This file is part of the VESC firmware.
The VESC firmware is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
The VESC firmware is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_A200S_V3_CORE_H_
#define HW_A200S_V3_CORE_H_
// HW properties
#define HW_USE_INTERNAL_RC
#define HW_HAS_PHASE_FILTERS
// Macros
/*
* ADC Vector
*
* 0 (1): IN0 SENS1
* 1 (2): IN1 SENS2
* 2 (3): IN2 SENS3
* 3 (1): IN10 CURR1
* 4 (2): IN11 CURR2
* 5 (3): IN12 5V_CURR
* 6 (1): IN5 ADC_EXT1
* 7 (2): IN6 ADC_EXT2
* 8 (3): IN3 TEMP_MOS
* 9 (1): IN14 TEMP_MOTOR
* 10 (2): IN15 ADC_EXT3
* 11 (3): IN13 AN_IN
* 12 (1): Vrefint
* 13 (2): IN0 SENS1
* 14 (3): IN1 SENS2
* 15 (1): IN8 TEMP_MOS_2
* 16 (2): IN9 TEMP_MOS_3
* 17 (3): IN3 SENS3
*/
#define HW_ADC_CHANNELS 18
#define HW_ADC_INJ_CHANNELS 3
#define HW_ADC_NBR_CONV 6
// ADC Indexes
#define ADC_IND_SENS1 0
#define ADC_IND_SENS2 1
#define ADC_IND_SENS3 2
#define ADC_IND_CURR1 3
#define ADC_IND_CURR2 4
#define ADC_IND_5V_CURR 5
#define ADC_IND_VIN_SENS 11
#define ADC_IND_EXT 6
#define ADC_IND_EXT2 7
#define ADC_IND_EXT3 10
#define ADC_IND_TEMP_MOS 8
#define ADC_IND_TEMP_MOS_2 15
#define ADC_IND_TEMP_MOS_3 16
#define ADC_IND_TEMP_MOTOR 9
#define ADC_IND_VREFINT 12
// ADC macros and settings
// Component parameters (can be overridden)
#ifndef V_REG
#define V_REG 3.30
#endif
#ifndef VIN_R1
#define VIN_R1 66000.0
#endif
#ifndef VIN_R2
#define VIN_R2 2200.0
#endif
#ifndef CURRENT_AMP_GAIN
#define CURRENT_AMP_GAIN 20.0
#endif
#ifndef CURRENT_SHUNT_RES
#define CURRENT_SHUNT_RES 0.0002
#endif
// Input voltage
#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2))
// NTC Termistors
#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0)
#define NTC_TEMP(adc_ind) hw_a200s_get_temp()
#define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side
#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15)
#define NTC_TEMP_MOS1() (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
#define NTC_TEMP_MOS2() hw_a200s_get_temp_mos()
#define NTC_TEMP_MOS3() hw_a200s_get_temp_shunt()
// Voltage on ADC channel
#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG)
// 5V Supply output current
#define GET_5V_OUTPUT_CURRENT() ((float)(ADC_VOLTS(ADC_IND_5V_CURR)))//((float)(ADC_VOLTS(ADC_IND_5V_CURR)-0.4)*2.778)
// Double samples in beginning and end for positive current measurement.
// Useful when the shunt sense traces have noise that causes offset.
#ifndef CURR1_DOUBLE_SAMPLE
#define CURR1_DOUBLE_SAMPLE 0
#endif
#ifndef CURR2_DOUBLE_SAMPLE
#define CURR2_DOUBLE_SAMPLE 0
#endif
#ifndef CURR3_DOUBLE_SAMPLE
#define CURR3_DOUBLE_SAMPLE 0
#endif
#define LED_GREEN_GPIO GPIOB
#define LED_GREEN_PIN 5
#define LED_RED_GPIO GPIOB
#define LED_RED_PIN 7
#define LED_GREEN_ON() palSetPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_GREEN_OFF() palClearPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_RED_ON() palSetPad(LED_RED_GPIO, LED_RED_PIN)
#define LED_RED_OFF() palClearPad(LED_RED_GPIO, LED_RED_PIN)
// Phase filter
#define PHASE_FILTER_OFF() palSetPad(GPIOC, 9); palSetPad(GPIOC, 13); palSetPad(GPIOC, 14)
#define PHASE_FILTER_ON() palClearPad(GPIOC, 9); palClearPad(GPIOC, 13); palClearPad(GPIOC, 14)
// Current filter - Disable even when told to go on, as this really won't help for low side shunts
// new hardware has no filter capacitor
#define CURRENT_FILTER_OFF() palSetPad(GPIOC, 15); palSetPad(GPIOB, 1)
#define CURRENT_FILTER_ON() palSetPad(GPIOC, 15); palSetPad(GPIOB, 1)
// Aux
#define AUX_GPIO GPIOC
#define AUX_PIN 12
#define AUX_ON() palSetPad(AUX_GPIO, AUX_PIN)
#define AUX_OFF() palClearPad(AUX_GPIO, AUX_PIN)
// COMM-port ADC GPIOs
#define HW_ADC_EXT_GPIO GPIOA
#define HW_ADC_EXT_PIN 5
#define HW_ADC_EXT2_GPIO GPIOA
#define HW_ADC_EXT2_PIN 6
// UART Peripheral
#define HW_UART_DEV SD3
#define HW_UART_GPIO_AF GPIO_AF_USART3
#define HW_UART_TX_PORT GPIOB
#define HW_UART_TX_PIN 10
#define HW_UART_RX_PORT GPIOB
#define HW_UART_RX_PIN 11
// SPI pins
#define HW_SPI_DEV SPID1
#define HW_SPI_GPIO_AF GPIO_AF_SPI1
#define HW_SPI_PORT_NSS GPIOB
#define HW_SPI_PIN_NSS 11
#define HW_SPI_PORT_SCK GPIOA
#define HW_SPI_PIN_SCK 5
#define HW_SPI_PORT_MOSI GPIOA
#define HW_SPI_PIN_MOSI 7
#define HW_SPI_PORT_MISO GPIOA
#define HW_SPI_PIN_MISO 6
// I2C Peripheral
#define HW_I2C_DEV I2CD2
#define HW_I2C_GPIO_AF GPIO_AF_I2C2
#define HW_I2C_SCL_PORT GPIOB
#define HW_I2C_SCL_PIN 10
#define HW_I2C_SDA_PORT GPIOB
#define HW_I2C_SDA_PIN 11
// Hall/encoder pins
#define HW_HALL_ENC_GPIO1 GPIOC
#define HW_HALL_ENC_PIN1 6
#define HW_HALL_ENC_GPIO2 GPIOC
#define HW_HALL_ENC_PIN2 7
#define HW_HALL_ENC_GPIO3 GPIOC
#define HW_HALL_ENC_PIN3 8
#define HW_ENC_TIM TIM3
#define HW_ENC_TIM_AF GPIO_AF_TIM3
#define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE)
#define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC
#define HW_ENC_EXTI_PINSRC EXTI_PinSource8
#define HW_ENC_EXTI_CH EXTI9_5_IRQn
#define HW_ENC_EXTI_LINE EXTI_Line8
#define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler
#define HW_ENC_TIM_ISR_CH TIM3_IRQn
#define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler
// BMX160
#define BMI160_SDA_GPIO GPIOB
#define BMI160_SDA_PIN 2
#define BMI160_SCL_GPIO GPIOA
#define BMI160_SCL_PIN 15
#define IMU_ROT_180
// Permanent UART Peripheral (for NRF51)
#define HW_UART_P_BAUD 115200
#define HW_UART_P_DEV SD4
#define HW_UART_P_GPIO_AF GPIO_AF_UART4
#define HW_UART_P_TX_PORT GPIOC
#define HW_UART_P_TX_PIN 10
#define HW_UART_P_RX_PORT GPIOC
#define HW_UART_P_RX_PIN 11
// NRF SWD
#define NRF5x_SWDIO_GPIO GPIOB
#define NRF5x_SWDIO_PIN 12
#define NRF5x_SWCLK_GPIO GPIOA
#define NRF5x_SWCLK_PIN 4
// ICU Peripheral for servo decoding
#define HW_USE_SERVO_TIM4
#define HW_ICU_TIMER TIM4
#define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE)
#define HW_ICU_DEV ICUD4
#define HW_ICU_CHANNEL ICU_CHANNEL_1
#define HW_ICU_GPIO_AF GPIO_AF_TIM4
#define HW_ICU_GPIO GPIOB
#define HW_ICU_PIN 6
// Measurement macros
#define ADC_V_L1 ADC_Value[ADC_IND_SENS1]
#define ADC_V_L2 ADC_Value[ADC_IND_SENS2]
#define ADC_V_L3 ADC_Value[ADC_IND_SENS3]
#define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2)
// Macros
#define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1)
#define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2)
#define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3)
// Default setting overrides
#ifndef MCCONF_L_MIN_VOLTAGE
#define MCCONF_L_MIN_VOLTAGE 10.0 // Minimum input voltage
#endif
#ifndef MCCONF_DEFAULT_MOTOR_TYPE
#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC
#endif
#ifndef MCCONF_FOC_F_ZV
#define MCCONF_FOC_F_ZV 30000.0
#endif
#define HW_LIM_FOC_CTRL_LOOP_FREQ 5000.0, 25000.0 //Limit to 50kHz max
#ifndef MCCONF_L_MAX_ABS_CURRENT
#define MCCONF_L_MAX_ABS_CURRENT 220.0 // The maximum absolute current above which a fault is generated
#endif
#ifndef MCCONF_FOC_SAMPLE_V0_V7
#define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts)
#endif
#ifndef MCCONF_L_CURRENT_MAX
#define MCCONF_L_CURRENT_MAX 100.0 // Current limit in Amperes (Upper)
#endif
#ifndef MCCONF_L_CURRENT_MIN
#define MCCONF_L_CURRENT_MIN -100.0 // Current limit in Amperes (Lower)
#endif
#ifndef MCCONF_L_SLOW_ABS_OVERCURRENT
#define MCCONF_L_SLOW_ABS_OVERCURRENT false // Use the raw current for the overcurrent fault detection
#endif
#ifndef MCCONF_L_IN_CURRENT_MAX
#define MCCONF_L_IN_CURRENT_MAX 50.0 // Input current limit in Amperes (Upper)
#endif
#ifndef MCCONF_L_IN_CURRENT_MIN
#define MCCONF_L_IN_CURRENT_MIN -20.0 // Input current limit in Amperes (Lower)
#endif
#define HW_NAME "A200S_V3"
// Mosfet and K/W for working out temperatures
#define HW_TEMP_MOSFET_R 0.0017f // Resistance of mosfets
#define HW_TEMP_MOSFET_KW 2.0f // Kelvin/Watt of mosfets
#define HW_TEMP_MOSFET_COUNT 3.0f // How many mosfets in parallel
#define HW_TEMP_SHUNT_KW 25.0f // Kelvin/Watt of shunts
#define HW_TEMP_NUM_PHASES 3.0f // How many phases
// Setting limits
#define HW_LIM_CURRENT -250.0, 250.0
#define HW_LIM_CURRENT_IN -200.0, 200.0 // 200A for 10 AWG inputs (2x 100A)
#define HW_LIM_CURRENT_ABS 0.0, 350.0
#define HW_LIM_VIN 6.0, 75.0
#define HW_LIM_ERPM -200e3, 200e3
#define HW_LIM_DUTY_MIN 0.0, 0.1
#define HW_LIM_DUTY_MAX 0.0, 0.98
#define HW_LIM_TEMP_FET -40.0, 100.0
#ifndef MCCONF_L_MAX_VOLTAGE
#define MCCONF_L_MAX_VOLTAGE 16.0 * 4.2 + 5.0 // Maximum input voltage
#endif
#ifndef MCCONF_FOC_DT_US
#define MCCONF_FOC_DT_US 0.1 // Microseconds for dead time compensation
#endif
// Override dead time. See the stm32f4 reference manual for calculating this value.
#define HW_DEAD_TIME_NSEC 800.0 // FD6288Q has 170ns built in deadtime
// HW-specific functions
float hw_a200s_get_temp_mos(void);
float hw_a200s_get_temp_shunt(void);
float hw_a200s_get_temp(void);
#endif /* HW_A200S_V3_CORE_H_ */

27
hwconf/teamtriforceuk/a200s_v4/hw_a200s_v4.h Normal file
View File

@ -0,0 +1,27 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This file is part of the VESC firmware.
The VESC firmware is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
The VESC firmware is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_A200S_V4_H_
#define HW_A200S_V4_H_
#define HW_A200S_V4
#include "hw_a200s_v4_core.h"
#endif /* HW_A200S_V4_H_ */

456
hwconf/teamtriforceuk/a200s_v4/hw_a200s_v4_core.c Normal file
View File

@ -0,0 +1,456 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "hw.h"
#include "ch.h"
#include "hal.h"
#include "stm32f4xx_conf.h"
#include "utils.h"
#include <math.h>
#include "mc_interface.h"
#include "commands.h"
#include "terminal.h"
#include "mcpwm.h"
#include "mcpwm_foc.h"
#include "gpdrive.h"
#include "app.h"
#include "mempools.h"
#include "timeout.h"
#include "stdio.h"
// Variables
static volatile bool i2c_running = false;
// Private functions
static void terminal_cmd_doublepulse(int argc, const char** argv);
// I2C configuration
static const I2CConfig i2cfg = {
OPMODE_I2C,
100000,
STD_DUTY_CYCLE
};
void hw_init_gpio(void) {
// GPIO clock enable
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
// LEDs
palSetPadMode(GPIOB, 5,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(GPIOB, 7,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
// HW protection pins
// Clear
palSetPadMode(HW_PROTECTION_CLEAR_GPIO, HW_PROTECTION_CLEAR_PIN,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
palClearPad(HW_PROTECTION_CLEAR_GPIO, HW_PROTECTION_CLEAR_PIN);
// Disable
palSetPadMode(GPIOC, 5,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
DISABLE_GATE();
#ifdef HW_USE_BRK
// BRK Fault pin
palSetPadMode(BRK_GPIO, BRK_PIN, PAL_MODE_ALTERNATE(GPIO_AF_TIM1));
#else
// Soft Lockout
palSetPadMode(BRK_GPIO, BRK_PIN, PAL_MODE_INPUT);
#endif
// AUX
AUX_OFF();
palSetPadMode(AUX_GPIO, AUX_PIN,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
// Output protection
palSetPadMode(HW_5V_FAULT_GPIO, HW_5V_FAULT_PIN, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_3V3_FAULT_GPIO, HW_3V3_FAULT_PIN, PAL_MODE_INPUT_PULLUP);
// GPIOA Configuration: Channel 1 to 3 as alternate function push-pull
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
PAL_STM32_OSPEED_HIGHEST |
PAL_STM32_PUDR_FLOATING);
// Hall sensors
palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP);
palSetPadMode(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, PAL_MODE_INPUT_PULLUP);
// Phase filters
palSetPadMode(GPIOC, 9, PAL_MODE_OUTPUT_OPENDRAIN);
palSetPadMode(GPIOC, 13, PAL_MODE_OUTPUT_OPENDRAIN);
palSetPadMode(GPIOC, 14, PAL_MODE_OUTPUT_OPENDRAIN);
PHASE_FILTER_OFF();
// ADC Pins
palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOB, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOB, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG);
palSetPadMode(GPIOC, 4, PAL_MODE_INPUT_ANALOG);
//register terminal callbacks
terminal_register_command_callback(
"double_pulse",
"Start a double pulse test",
0,
terminal_cmd_doublepulse);
}
void hw_setup_adc_channels(void) {
// ADC1 regular channels
ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles); // 0 - ADC_IND_CURR1
ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 2, ADC_SampleTime_15Cycles); // 3 - ADC_IND_SENS1
ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 3, ADC_SampleTime_15Cycles); // 6 - ADC_IND_EXT
ADC_RegularChannelConfig(ADC1, ADC_Channel_Vrefint, 4, ADC_SampleTime_15Cycles); // 9 - ADC_IND_VREFINT
ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 5, ADC_SampleTime_15Cycles); // 12 - ADC_IND_TEMP_MOS_2
ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 6, ADC_SampleTime_15Cycles); // 15 - ADC_IND_TEMP_MOTOR
// ADC2 regular channels
ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles); // 1 - ADC_IND_CURR2
ADC_RegularChannelConfig(ADC2, ADC_Channel_1, 2, ADC_SampleTime_15Cycles); // 4 - ADC_IND_SENS2
ADC_RegularChannelConfig(ADC2, ADC_Channel_6, 3, ADC_SampleTime_15Cycles); // 7 - ADC_IND_EXT2
ADC_RegularChannelConfig(ADC2, ADC_Channel_15, 4, ADC_SampleTime_15Cycles); // 10 - ADC_IND_EXT3
ADC_RegularChannelConfig(ADC2, ADC_Channel_9, 5, ADC_SampleTime_15Cycles); // 13 - ADC_IND_TEMP_MOS_3
ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 6, ADC_SampleTime_15Cycles); // 16 - UNUSED -- placeholder
// ADC3 regular channels - only a subset of channels avaliable
ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles); // 2 - ADC_IND_CURR3
ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 2, ADC_SampleTime_15Cycles); // 5 - ADC_IND_SENS3
ADC_RegularChannelConfig(ADC3, ADC_Channel_13, 3, ADC_SampleTime_15Cycles); // 8 - ADC_IND_VIN_SENS
ADC_RegularChannelConfig(ADC3, ADC_Channel_3, 4, ADC_SampleTime_15Cycles); // 11 - ADC_IND_TEMP_MOS
ADC_RegularChannelConfig(ADC3, ADC_Channel_1, 5, ADC_SampleTime_15Cycles); // 14 - UNUSED -- placeholder
ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 6, ADC_SampleTime_15Cycles); // 17 - UNUSED -- placeholder
// Injected channels
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles); // ADC_IND_CURR1
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles); // ADC_IND_CURR2
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles); // ADC_IND_CURR3
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles); // ADC_IND_CURR1
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles); // ADC_IND_CURR2
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles); // ADC_IND_CURR3
ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 3, ADC_SampleTime_15Cycles); // ADC_IND_CURR1
ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 3, ADC_SampleTime_15Cycles); // ADC_IND_CURR2
ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles); // ADC_IND_CURR3
}
void hw_start_i2c(void) {
i2cAcquireBus(&HW_I2C_DEV);
if (!i2c_running) {
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
i2cStart(&HW_I2C_DEV, &i2cfg);
i2c_running = true;
}
i2cReleaseBus(&HW_I2C_DEV);
}
void hw_stop_i2c(void) {
i2cAcquireBus(&HW_I2C_DEV);
if (i2c_running) {
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, PAL_MODE_INPUT);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, PAL_MODE_INPUT);
i2cStop(&HW_I2C_DEV);
i2c_running = false;
}
i2cReleaseBus(&HW_I2C_DEV);
}
/**
* Try to restore the i2c bus
*/
void hw_try_restore_i2c(void) {
if (i2c_running) {
i2cAcquireBus(&HW_I2C_DEV);
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
chThdSleep(1);
for(int i = 0;i < 16;i++) {
palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
}
// Generate start then stop condition
palClearPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
chThdSleep(1);
palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
chThdSleep(1);
palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
PAL_STM32_OTYPE_OPENDRAIN |
PAL_STM32_OSPEED_MID1 |
PAL_STM32_PUDR_PULLUP);
HW_I2C_DEV.state = I2C_STOP;
i2cStart(&HW_I2C_DEV, &i2cfg);
i2cReleaseBus(&HW_I2C_DEV);
}
}
float hw_a200s_get_temp(void) {
float t1 = (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15);
float t2 = (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS_2]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15);
float t3 = (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS_3]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15);
float res = 0.0;
if (t1 > t2 && t1 > t3) {
res = t1;
} else if (t2 > t1 && t2 > t3) {
res = t2;
} else {
res = t3;
}
return res;
}
void hw_a200s_reset_faults(void) {
palSetPad(HW_PROTECTION_CLEAR_GPIO, HW_PROTECTION_CLEAR_PIN);
chThdSleep(100);
palClearPad(HW_PROTECTION_CLEAR_GPIO, HW_PROTECTION_CLEAR_PIN);
}
static void terminal_cmd_doublepulse(int argc, const char** argv)
{
(void)argc;
(void)argv;
int preface, pulse1, breaktime, pulse2;
int utick;
int deadtime = -1;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
if (argc < 5) {
commands_printf("Usage: double_pulse <preface> <pulse1> <break> <pulse2> [deadtime]");
commands_printf(" preface: idle time in us");
commands_printf(" pulse1: high time of pulse 1 in us");
commands_printf(" break: break between pulses in us");
commands_printf(" pulse2: high time of pulse 2 in us");
commands_printf(" deadtime: overwrite deadtime, in ns");
return;
}
sscanf(argv[1], "%d", &preface);
sscanf(argv[2], "%d", &pulse1);
sscanf(argv[3], "%d", &breaktime);
sscanf(argv[4], "%d", &pulse2);
if (argc == 6) {
sscanf(argv[5], "%d", &deadtime);
}
timeout_configure_IWDT_slowest();
utick = (int)(SYSTEM_CORE_CLOCK / 1000000);
mcpwm_deinit();
mcpwm_foc_deinit();
gpdrive_deinit();
TIM_Cmd(TIM1, DISABLE);
TIM_Cmd(TIM4, DISABLE);
//TIM4 als Trigger Timer
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
TIM_TimeBaseStructure.TIM_Period = (SYSTEM_CORE_CLOCK / 20000);
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
TIM_SelectMasterSlaveMode(TIM4, TIM_MasterSlaveMode_Enable);
TIM_SelectOutputTrigger(TIM4, TIM_TRGOSource_Enable);
TIM4->CNT = 0;
// TIM1
// TIM1 clock enable
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
// Time Base configuration
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = (preface + pulse1) * utick;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
// Channel 1, 2 and 3 Configuration in PWM mode
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_Pulse = preface * utick;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC2Init(TIM1, &TIM_OCInitStructure);
TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_OC3Init(TIM1, &TIM_OCInitStructure);
TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM2);
TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_Inactive);
TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable);
TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_Inactive);
TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable);
TIM_GenerateEvent(TIM1, TIM_EventSource_COM);
// Automatic Output enable, Break, dead time and lock configuration
TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
if (deadtime < 0) {
TIM_BDTRInitStructure.TIM_DeadTime = conf_general_calculate_deadtime(HW_DEAD_TIME_NSEC, SYSTEM_CORE_CLOCK);
} else {
TIM_BDTRInitStructure.TIM_DeadTime = conf_general_calculate_deadtime(deadtime, SYSTEM_CORE_CLOCK);
}
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
TIM_CCPreloadControl(TIM1, ENABLE);
TIM_ARRPreloadConfig(TIM1, ENABLE);
TIM1->CNT = 0;
TIM1->EGR = TIM_EGR_UG;
TIM_SelectSlaveMode(TIM1, TIM_SlaveMode_Trigger);
TIM_SelectInputTrigger(TIM1, TIM_TS_ITR3);
TIM_SelectOnePulseMode(TIM1, TIM_OPMode_Single);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
TIM_Cmd(TIM1, ENABLE);
//Timer 4 triggert Timer 1
TIM_Cmd(TIM4, ENABLE);
TIM_Cmd(TIM4, DISABLE);
TIM1->ARR = (breaktime + pulse2) * utick;
TIM1->CCR1 = breaktime * utick;
while (TIM1->CNT != 0);
TIM_Cmd(TIM4, ENABLE);
chThdSleepMilliseconds(1);
TIM_CtrlPWMOutputs(TIM1, DISABLE);
mc_configuration* mcconf = mempools_alloc_mcconf();
*mcconf = *mc_interface_get_configuration();
switch (mcconf->motor_type) {
case MOTOR_TYPE_BLDC:
case MOTOR_TYPE_DC:
mcpwm_init(mcconf);
break;
case MOTOR_TYPE_FOC:
mcpwm_foc_init(mcconf, mcconf);
break;
case MOTOR_TYPE_GPD:
gpdrive_init(mcconf);
break;
default:
break;
}
commands_printf("Done");
return;
}

295
hwconf/teamtriforceuk/a200s_v4/hw_a200s_v4_core.h Normal file
View File

@ -0,0 +1,295 @@
/*
Copyright 2018 Benjamin Vedder benjamin@vedder.se
This file is part of the VESC firmware.
The VESC firmware is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
The VESC firmware is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_A200S_V4_CORE_H_
#define HW_A200S_V4_CORE_H_
// HW properties
#define HW_HAS_3_SHUNTS
#define INVERTED_SHUNT_POLARITY
#define HW_HAS_PHASE_FILTERS
#define HW_USE_25MHZ_EXT_CLOCK
#define HW_HAS_LV_OUTPUT_PROTECTION
#define HW_ADC_CHANNELS 18
#define HW_ADC_INJ_CHANNELS 3
#define HW_ADC_NBR_CONV 6
// ADC Indexes - refer to .c for descriptions
#define ADC_IND_CURR1 0
#define ADC_IND_CURR2 1
#define ADC_IND_CURR3 2
#define ADC_IND_VIN_SENS 8
#define ADC_IND_SENS1 3
#define ADC_IND_SENS2 4
#define ADC_IND_SENS3 5
#define ADC_IND_EXT 6
#define ADC_IND_EXT2 7
#define ADC_IND_EXT3 10
#define ADC_IND_TEMP_MOS 11
#define ADC_IND_TEMP_MOS_2 12
#define ADC_IND_TEMP_MOS_3 13
#define ADC_IND_TEMP_MOTOR 15
#define ADC_IND_VREFINT 9
// ADC macros and settings
// Component parameters (can be overridden)
#ifndef V_REG
#define V_REG 3.30
#endif
#ifndef VIN_R1
#define VIN_R1 68000.0
#endif
#ifndef VIN_R2
#define VIN_R2 2200.0
#endif
#ifndef CURRENT_AMP_GAIN
#define CURRENT_AMP_GAIN 20.0
#endif
#ifndef CURRENT_SHUNT_RES
#define CURRENT_SHUNT_RES (0.0002)
#endif
// Input voltage
#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2))
// NTC Termistors
#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0)
#define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side
#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15)
#define NTC_TEMP(adc_ind) hw_a200s_get_temp()
#define NTC_TEMP_MOS1() (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
#define NTC_TEMP_MOS2() (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS_2]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
#define NTC_TEMP_MOS3() (1.0 / ((logf(NTC_RES(ADC_Value[ADC_IND_TEMP_MOS_3]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
// Voltage on ADC channel
#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG)
// Double samples in beginning and end for positive current measurement.
// Useful when the shunt sense traces have noise that causes offset.
#ifndef CURR1_DOUBLE_SAMPLE
#define CURR1_DOUBLE_SAMPLE 0
#endif
#ifndef CURR2_DOUBLE_SAMPLE
#define CURR2_DOUBLE_SAMPLE 0
#endif
#ifndef CURR3_DOUBLE_SAMPLE
#define CURR3_DOUBLE_SAMPLE 0
#endif
#define LED_GREEN_GPIO GPIOB
#define LED_GREEN_PIN 5
#define LED_RED_GPIO GPIOB
#define LED_RED_PIN 7
#define LED_GREEN_ON() palSetPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_GREEN_OFF() palClearPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_RED_ON() palSetPad(LED_RED_GPIO, LED_RED_PIN)
#define LED_RED_OFF() palClearPad(LED_RED_GPIO, LED_RED_PIN)
// Aux - TCKE812NA,RF
#define AUX_GPIO GPIOC
#define AUX_PIN 15
#define AUX_ON() palSetPad(AUX_GPIO, AUX_PIN)
#define AUX_OFF() palClearPad(AUX_GPIO, AUX_PIN)
// Phase filter
#define PHASE_FILTER_OFF() palSetPad(GPIOC, 9); palSetPad(GPIOC, 13); palSetPad(GPIOC, 14)
#define PHASE_FILTER_ON() palClearPad(GPIOC, 9); palClearPad(GPIOC, 13); palClearPad(GPIOC, 14)
// COMM-port ADC GPIOs
#define HW_ADC_EXT_GPIO GPIOA
#define HW_ADC_EXT_PIN 5
#define HW_ADC_EXT2_GPIO GPIOA
#define HW_ADC_EXT2_PIN 6
// UART Peripheral
#define HW_UART_DEV SD3
#define HW_UART_GPIO_AF GPIO_AF_USART3
#define HW_UART_TX_PORT GPIOB
#define HW_UART_TX_PIN 10
#define HW_UART_RX_PORT GPIOB
#define HW_UART_RX_PIN 11
// SPI pins
#define HW_SPI_DEV SPID1
#define HW_SPI_GPIO_AF GPIO_AF_SPI1
#define HW_SPI_PORT_NSS GPIOB
#define HW_SPI_PIN_NSS 11
#define HW_SPI_PORT_SCK GPIOA
#define HW_SPI_PIN_SCK 5
#define HW_SPI_PORT_MOSI GPIOA
#define HW_SPI_PIN_MOSI 7
#define HW_SPI_PORT_MISO GPIOA
#define HW_SPI_PIN_MISO 6
// I2C Peripheral
#define HW_I2C_DEV I2CD2
#define HW_I2C_GPIO_AF GPIO_AF_I2C2
#define HW_I2C_SCL_PORT GPIOB
#define HW_I2C_SCL_PIN 10
#define HW_I2C_SDA_PORT GPIOB
#define HW_I2C_SDA_PIN 11
// Hall/encoder pins
#define HW_HALL_ENC_GPIO1 GPIOC
#define HW_HALL_ENC_PIN1 6
#define HW_HALL_ENC_GPIO2 GPIOC
#define HW_HALL_ENC_PIN2 7
#define HW_HALL_ENC_GPIO3 GPIOC
#define HW_HALL_ENC_PIN3 8
#define HW_ENC_TIM TIM3
#define HW_ENC_TIM_AF GPIO_AF_TIM3
#define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE)
#define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC
#define HW_ENC_EXTI_PINSRC EXTI_PinSource8
#define HW_ENC_EXTI_CH EXTI9_5_IRQn
#define HW_ENC_EXTI_LINE EXTI_Line8
#define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler
#define HW_ENC_TIM_ISR_CH TIM3_IRQn
#define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler
// Permanent UART Peripheral (for Logger)
#define HW_UART_P_BAUD 1000000
#define HW_UART_P_DEV SD4
#define HW_UART_P_GPIO_AF GPIO_AF_UART4
#define HW_UART_P_TX_PORT GPIOC
#define HW_UART_P_TX_PIN 10
#define HW_UART_P_RX_PORT GPIOC
#define HW_UART_P_RX_PIN 11
// ICU Peripheral for servo decoding
#define HW_USE_SERVO_TIM4
#define HW_ICU_TIMER TIM4
#define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE)
#define HW_ICU_DEV ICUD4
#define HW_ICU_CHANNEL ICU_CHANNEL_1
#define HW_ICU_GPIO_AF GPIO_AF_TIM4
#define HW_ICU_GPIO GPIOB
#define HW_ICU_PIN 6
// I2C for IMU
#define LSM6DS3_SDA_GPIO GPIOC
#define LSM6DS3_SDA_PIN 12
#define LSM6DS3_SCL_GPIO GPIOA
#define LSM6DS3_SCL_PIN 4
// Hardware protection
#define HW_RESET_DRV_FAULTS() hw_a200s_reset_faults()
#define HW_PROTECTION_CLEAR_GPIO GPIOB
#define HW_PROTECTION_CLEAR_PIN 4
#define HW_5V_FAULT_GPIO GPIOB
#define HW_5V_FAULT_PIN 3
#define HW_3V3_FAULT_GPIO GPIOD
#define HW_3V3_FAULT_PIN 2
#define ENABLE_GATE() palClearPad(GPIOC, 5)
#define DISABLE_GATE() palSetPad(GPIOC, 5)
#define IS_DRV_FAULT() (palReadPad(GPIOB, 12))
#define IS_LV_OUTPUT_FAULT() !(palReadPad(HW_5V_FAULT_GPIO, HW_5V_FAULT_PIN) && palReadPad(HW_3V3_FAULT_GPIO, HW_3V3_FAULT_PIN))
#define BRK_GPIO GPIOB
#define BRK_PIN 12
// Measurement macros
#define ADC_V_L1 ADC_Value[ADC_IND_SENS1]
#define ADC_V_L2 ADC_Value[ADC_IND_SENS2]
#define ADC_V_L3 ADC_Value[ADC_IND_SENS3]
#define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2)
// Macros
#define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1)
#define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2)
#define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3)
// Default setting overrides
#ifndef MCCONF_L_MIN_VOLTAGE
#define MCCONF_L_MIN_VOLTAGE 14.0 // Minimum input voltage
#endif
#ifndef MCCONF_DEFAULT_MOTOR_TYPE
#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC
#endif
#ifndef MCCONF_FOC_F_ZV
#define MCCONF_FOC_F_ZV 30000.0
#endif
#define HW_LIM_FOC_CTRL_LOOP_FREQ 5000.0, 25000.0 //Limit to 50kHz max
#ifndef MCCONF_L_MAX_ABS_CURRENT
#define MCCONF_L_MAX_ABS_CURRENT 200.0 // The maximum absolute current above which a fault is generated
#endif
#ifndef MCCONF_FOC_SAMPLE_V0_V7
#define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts)
#endif
#ifndef MCCONF_L_CURRENT_MAX
#define MCCONF_L_CURRENT_MAX 100.0 // Current limit in Amperes (Upper)
#endif
#ifndef MCCONF_L_CURRENT_MIN
#define MCCONF_L_CURRENT_MIN -100.0 // Current limit in Amperes (Lower)
#endif
#ifndef MCCONF_L_SLOW_ABS_OVERCURRENT
#define MCCONF_L_SLOW_ABS_OVERCURRENT false // Use the raw current for the overcurrent fault detection
#endif
#ifndef MCCONF_L_IN_CURRENT_MAX
#define MCCONF_L_IN_CURRENT_MAX 20.0 // Input current limit in Amperes (Upper)
#endif
#ifndef MCCONF_L_IN_CURRENT_MIN
#define MCCONF_L_IN_CURRENT_MIN -5.0 // Input current limit in Amperes (Lower)
#endif
// Mosfet and K/W for working out temperatures
#define HW_TEMP_MOSFET_R 0.0017f // Resistance of mosfets
#define HW_TEMP_MOSFET_KW 2.0f // Kelvin/Watt of mosfets
#define HW_TEMP_MOSFET_COUNT 3.0f // How many mosfets in parallel
#define HW_TEMP_SHUNT_KW 25.0f // Kelvin/Watt of shunts
#define HW_TEMP_NUM_PHASES 3.0f // How many phases
// Setting limits
#define HW_NAME "A200S_V4"
#define HW_LIM_CURRENT -250.0, 250.0
#define HW_LIM_CURRENT_IN -180.0, 180.0
#define HW_LIM_CURRENT_ABS 0.0, 350.0
#define HW_LIM_VIN -1.0, 80.0
#define HW_LIM_ERPM -200e3, 200e3
#define HW_LIM_DUTY_MIN 0.0, 0.1
#define HW_LIM_DUTY_MAX 0.0, 0.98
#define HW_LIM_TEMP_FET -40.0, 110.0
#ifndef MCCONF_L_MAX_VOLTAGE
#define MCCONF_L_MAX_VOLTAGE 16.0 * 4.2 + 5.0 // Maximum input voltage
#endif
#ifndef MCCONF_FOC_DT_US
#define MCCONF_FOC_DT_US 0.1 // Microseconds for dead time compensation
#endif
#define HW_DEAD_TIME_NSEC 600.0
// HW-specific functions
float hw_a200s_get_temp(void);
void hw_a200s_set_curr_trip(uint16_t);
void hw_a200s_reset_faults(void);
#endif /* HW_A200S_V4_CORE_H_ */

3
hwconf/teamtriforceuk/a50s/hw_a50s_12s.h
View File

@ -3,6 +3,9 @@
#define HW_A50S_12S #define HW_A50S_12S
#define HW_NAME "a50s_12s"
#define CURRENT_AMP_GAIN 20.0
#include "hw_a50s_core.h" #include "hw_a50s_core.h"
#endif /* HW_A50S_12S_H_ */ #endif /* HW_A50S_12S_H_ */

11
hwconf/teamtriforceuk/a50s/hw_a50s_12s_hg.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef HW_A50S_12S_H_
#define HW_A50S_12S_H_
#define HW_A50S_12S
#define HW_NAME "a50s_12s_hg"
#define CURRENT_AMP_GAIN 50.0
#include "hw_a50s_core.h"
#endif /* HW_A50S_12S_HG_H_ */

3
hwconf/teamtriforceuk/a50s/hw_a50s_6s.h
View File

@ -3,6 +3,9 @@
#define HW_A50S_6S #define HW_A50S_6S
#define HW_NAME "a50s_6s"
#define CURRENT_AMP_GAIN 20.0
#include "hw_a50s_core.h" #include "hw_a50s_core.h"
#endif /* HW_A50S_6S_H_ */ #endif /* HW_A50S_6S_H_ */

11
hwconf/teamtriforceuk/a50s/hw_a50s_6s_hg.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef HW_A50S_6S_H_
#define HW_A50S_6S_H_
#define HW_A50S_6S
#define HW_NAME "a50s_6s_hg"
#define CURRENT_AMP_GAIN 50.0
#include "hw_a50s_core.h"
#endif /* HW_A50S_6S_HG_H_ */

28
hwconf/teamtriforceuk/a50s/hw_a50s_core.c
View File

@ -2,18 +2,18 @@
Copyright 2018 Benjamin Vedder benjamin@vedder.se Copyright 2018 Benjamin Vedder benjamin@vedder.se
This program is free software: you can redistribute it and/or modify This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or the Free Software Foundation, either version 3 of the License, or
(at your option) any later version. (at your option) any later version.
This program is distributed in the hope that it will be useful, This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. GNU General Public License for more details.
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include "hw.h" #include "hw.h"
@ -82,10 +82,10 @@ void hw_init_gpio(void) {
palSetPadMode(GPIOB, 5, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); palSetPadMode(GPIOB, 5, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST);
PHASE_FILTER_OFF(); PHASE_FILTER_OFF();
// Current filter // Current filter, no use on low side shunts
palSetPadMode(GPIOH, 1, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); //palSetPadMode(GPIOH, 1, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); //palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST);
CURRENT_FILTER_ON(); //CURRENT_FILTER_ON();
// AUX pin // AUX pin
AUX_OFF(); AUX_OFF();

264
hwconf/teamtriforceuk/a50s/hw_a50s_core.h
View File

@ -4,50 +4,48 @@
This file is part of the VESC firmware. This file is part of the VESC firmware.
The VESC firmware is free software: you can redistribute it and/or modify The VESC firmware is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or the Free Software Foundation, either version 3 of the License, or
(at your option) any later version. (at your option) any later version.
The VESC firmware is distributed in the hope that it will be useful, The VESC firmware is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. GNU General Public License for more details.
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef HW_A50S_CORE_H_ #ifndef HW_A50S_CORE_H_
#define HW_A50S_CORE_H_ #define HW_A50S_CORE_H_
#define HW_HAS_PHASE_FILTERS
// HW properties // HW properties
#define HW_USE_INTERNAL_RC #define HW_USE_INTERNAL_RC
#define HW_HAS_PHASE_FILTERS
// Macros // Macros
/* /*
* ADC Vector * ADC Vector
* *
* 0 (1): IN0 SENS1 * 0 (1): IN0 SENS1
* 1 (2): IN1 SENS2 * 1 (2): IN1 SENS2
* 2 (3): IN2 SENS3 * 2 (3): IN2 SENS3
* 3 (1): IN10 CURR1 * 3 (1): IN10 CURR1
* 4 (2): IN11 CURR2 * 4 (2): IN11 CURR2
* 5 (3): IN12 CURR3 (not used) * 5 (3): IN12 CURR3 (not used)
* 6 (1): IN5 ADC_EXT1 * 6 (1): IN5 ADC_EXT1
* 7 (2): IN6 ADC_EXT2 * 7 (2): IN6 ADC_EXT2
* 8 (3): IN3 TEMP_MOS * 8 (3): IN3 TEMP_MOS
* 9 (1): IN14 TEMP_MOTOR * 9 (1): IN14 TEMP_MOTOR
* 10 (2): IN15 ADC_EXT3 * 10 (2): IN15 ADC_EXT3
* 11 (3): IN13 AN_IN * 11 (3): IN13 AN_IN
* 12 (1): Vrefint * 12 (1): Vrefint
* 13 (2): IN0 SENS1 * 13 (2): IN0 SENS1
* 14 (3): IN1 SENS2 * 14 (3): IN1 SENS2
* 15 (1): IN8 TEMP_MOS_2 * 15 (1): IN8 TEMP_MOS_2
* 16 (2): IN9 TEMP_MOS_3 * 16 (2): IN9 TEMP_MOS_3
* 17 (3): IN3 SENS3 * 17 (3): IN3 SENS3
*/ */
#define HW_ADC_CHANNELS 18 #define HW_ADC_CHANNELS 18
@ -62,7 +60,7 @@
#define ADC_IND_CURR2 3 #define ADC_IND_CURR2 3
#define ADC_IND_CURR3 5 #define ADC_IND_CURR3 5
#define ADC_IND_VIN_SENS 11 #define ADC_IND_VIN_SENS 11
#define ADC_IND_EXT 6 #define ADC_IND_EXT 6
#define ADC_IND_EXT2 7 #define ADC_IND_EXT2 7
#define ADC_IND_EXT3 10 #define ADC_IND_EXT3 10
#define ADC_IND_TEMP_MOS 8 #define ADC_IND_TEMP_MOS 8
@ -75,175 +73,165 @@
// Component parameters (can be overridden) // Component parameters (can be overridden)
#ifndef V_REG #ifndef V_REG
#define V_REG 3.30 #define V_REG 3.30
#endif #endif
#ifndef VIN_R1 #ifndef VIN_R1
#define VIN_R1 12000.0 #define VIN_R1 12000.0
#endif #endif
#ifndef VIN_R2 #ifndef VIN_R2
#define VIN_R2 620.0 #define VIN_R2 620.0
#endif #endif
#ifndef CURRENT_AMP_GAIN #ifndef CURRENT_AMP_GAIN
#define CURRENT_AMP_GAIN 20.0 #define CURRENT_AMP_GAIN 50.0
#endif #endif
#ifndef CURRENT_SHUNT_RES #ifndef CURRENT_SHUNT_RES
#define CURRENT_SHUNT_RES 0.0005 #define CURRENT_SHUNT_RES 0.0005
#endif #endif
// Input voltage // Input voltage
#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2)) #define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2))
// NTC Termistors // NTC Termistors
#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0) #define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0)
#define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15) #define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
#define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side #define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side
#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15) #define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15)
// Voltage on ADC channel // Voltage on ADC channel
#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG) #define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG)
// Double samples in beginning and end for positive current measurement. // Double samples in beginning and end for positive current measurement.
// Useful when the shunt sense traces have noise that causes offset. // Useful when the shunt sense traces have noise that causes offset.
#ifndef CURR1_DOUBLE_SAMPLE #ifndef CURR1_DOUBLE_SAMPLE
#define CURR1_DOUBLE_SAMPLE 0 #define CURR1_DOUBLE_SAMPLE 0
#endif #endif
#ifndef CURR2_DOUBLE_SAMPLE #ifndef CURR2_DOUBLE_SAMPLE
#define CURR2_DOUBLE_SAMPLE 0 #define CURR2_DOUBLE_SAMPLE 0
#endif #endif
#ifndef CURR3_DOUBLE_SAMPLE #ifndef CURR3_DOUBLE_SAMPLE
#define CURR3_DOUBLE_SAMPLE 0 #define CURR3_DOUBLE_SAMPLE 0
#endif #endif
// Unused // Unused
#define LED_GREEN_GPIO GPIOB #define LED_GREEN_GPIO GPIOB
#define LED_GREEN_PIN 0 #define LED_GREEN_PIN 0
#define LED_RED_GPIO GPIOB #define LED_RED_GPIO GPIOB
#define LED_RED_PIN 1 #define LED_RED_PIN 1
#define LED_GREEN_ON() palSetPad(LED_GREEN_GPIO, LED_GREEN_PIN) #define LED_GREEN_ON() palSetPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_GREEN_OFF() palClearPad(LED_GREEN_GPIO, LED_GREEN_PIN) #define LED_GREEN_OFF() palClearPad(LED_GREEN_GPIO, LED_GREEN_PIN)
#define LED_RED_ON() palSetPad(LED_RED_GPIO, LED_RED_PIN) #define LED_RED_ON() palSetPad(LED_RED_GPIO, LED_RED_PIN)
#define LED_RED_OFF() palClearPad(LED_RED_GPIO, LED_RED_PIN) #define LED_RED_OFF() palClearPad(LED_RED_GPIO, LED_RED_PIN)
// Phase filter // Phase filter
#define PHASE_FILTER_OFF() palSetPad(GPIOB, 3); palSetPad(GPIOB, 4); palSetPad(GPIOB, 5) #define PHASE_FILTER_OFF() palSetPad(GPIOB, 3); palSetPad(GPIOB, 4); palSetPad(GPIOB, 5)
#define PHASE_FILTER_ON() palClearPad(GPIOB, 3); palClearPad(GPIOB, 4); palClearPad(GPIOB, 5) #define PHASE_FILTER_ON() palClearPad(GPIOB, 3); palClearPad(GPIOB, 4); palClearPad(GPIOB, 5)
// Current filter
#define CURRENT_FILTER_OFF() palSetPad(GPIOH, 1); palSetPad(GPIOC, 2)
#define CURRENT_FILTER_ON() palClearPad(GPIOH, 1); palClearPad(GPIOC, 2)
// Aux // Aux
#define AUX_GPIO GPIOC #define AUX_GPIO GPIOC
#define AUX_PIN 12 #define AUX_PIN 12
#define AUX_ON() palSetPad(AUX_GPIO, AUX_PIN) #define AUX_ON() palSetPad(AUX_GPIO, AUX_PIN)
#define AUX_OFF() palClearPad(AUX_GPIO, AUX_PIN) #define AUX_OFF() palClearPad(AUX_GPIO, AUX_PIN)
// COMM-port ADC GPIOs // COMM-port ADC GPIOs
#define HW_ADC_EXT_GPIO GPIOA #define HW_ADC_EXT_GPIO GPIOA
#define HW_ADC_EXT_PIN 5 #define HW_ADC_EXT_PIN 5
#define HW_ADC_EXT2_GPIO GPIOA #define HW_ADC_EXT2_GPIO GPIOA
#define HW_ADC_EXT2_PIN 6 #define HW_ADC_EXT2_PIN 6
// UART Peripheral // UART Peripheral
#define HW_UART_DEV SD3 #define HW_UART_DEV SD3
#define HW_UART_GPIO_AF GPIO_AF_USART3 #define HW_UART_GPIO_AF GPIO_AF_USART3
#define HW_UART_TX_PORT GPIOB #define HW_UART_TX_PORT GPIOB
#define HW_UART_TX_PIN 10 #define HW_UART_TX_PIN 10
#define HW_UART_RX_PORT GPIOB #define HW_UART_RX_PORT GPIOB
#define HW_UART_RX_PIN 11 #define HW_UART_RX_PIN 11
// SPI pins // SPI pins
#define HW_SPI_DEV SPID1 #define HW_SPI_DEV SPID1
#define HW_SPI_GPIO_AF GPIO_AF_SPI1 #define HW_SPI_GPIO_AF GPIO_AF_SPI1
#define HW_SPI_PORT_NSS GPIOB #define HW_SPI_PORT_NSS GPIOB
#define HW_SPI_PIN_NSS 11 #define HW_SPI_PIN_NSS 11
#define HW_SPI_PORT_SCK GPIOA #define HW_SPI_PORT_SCK GPIOA
#define HW_SPI_PIN_SCK 5 #define HW_SPI_PIN_SCK 5
#define HW_SPI_PORT_MOSI GPIOA #define HW_SPI_PORT_MOSI GPIOA
#define HW_SPI_PIN_MOSI 7 #define HW_SPI_PIN_MOSI 7
#define HW_SPI_PORT_MISO GPIOA #define HW_SPI_PORT_MISO GPIOA
#define HW_SPI_PIN_MISO 6 #define HW_SPI_PIN_MISO 6
// I2C Peripheral // I2C Peripheral
#define HW_I2C_DEV I2CD2 #define HW_I2C_DEV I2CD2
#define HW_I2C_GPIO_AF GPIO_AF_I2C2 #define HW_I2C_GPIO_AF GPIO_AF_I2C2
#define HW_I2C_SCL_PORT GPIOB #define HW_I2C_SCL_PORT GPIOB
#define HW_I2C_SCL_PIN 10 #define HW_I2C_SCL_PIN 10
#define HW_I2C_SDA_PORT GPIOB #define HW_I2C_SDA_PORT GPIOB
#define HW_I2C_SDA_PIN 11 #define HW_I2C_SDA_PIN 11
// Hall/encoder pins // Hall/encoder pins
#define HW_HALL_ENC_GPIO1 GPIOC #define HW_HALL_ENC_GPIO1 GPIOC
#define HW_HALL_ENC_PIN1 6 #define HW_HALL_ENC_PIN1 6
#define HW_HALL_ENC_GPIO2 GPIOC #define HW_HALL_ENC_GPIO2 GPIOC
#define HW_HALL_ENC_PIN2 7 #define HW_HALL_ENC_PIN2 7
#define HW_HALL_ENC_GPIO3 GPIOC #define HW_HALL_ENC_GPIO3 GPIOC
#define HW_HALL_ENC_PIN3 8 #define HW_HALL_ENC_PIN3 8
#define HW_ENC_TIM TIM3 #define HW_ENC_TIM TIM3
#define HW_ENC_TIM_AF GPIO_AF_TIM3 #define HW_ENC_TIM_AF GPIO_AF_TIM3
#define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE) #define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE)
#define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC #define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC
#define HW_ENC_EXTI_PINSRC EXTI_PinSource8 #define HW_ENC_EXTI_PINSRC EXTI_PinSource8
#define HW_ENC_EXTI_CH EXTI9_5_IRQn #define HW_ENC_EXTI_CH EXTI9_5_IRQn
#define HW_ENC_EXTI_LINE EXTI_Line8 #define HW_ENC_EXTI_LINE EXTI_Line8
#define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler #define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler
#define HW_ENC_TIM_ISR_CH TIM3_IRQn #define HW_ENC_TIM_ISR_CH TIM3_IRQn
#define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler #define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler
// ICU Peripheral for servo decoding // ICU Peripheral for servo decoding
#define HW_USE_SERVO_TIM4 #define HW_USE_SERVO_TIM4
#define HW_ICU_TIMER TIM4 #define HW_ICU_TIMER TIM4
#define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE) #define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE)
#define HW_ICU_DEV ICUD4 #define HW_ICU_DEV ICUD4
#define HW_ICU_CHANNEL ICU_CHANNEL_1 #define HW_ICU_CHANNEL ICU_CHANNEL_1
#define HW_ICU_GPIO_AF GPIO_AF_TIM4 #define HW_ICU_GPIO_AF GPIO_AF_TIM4
#define HW_ICU_GPIO GPIOB #define HW_ICU_GPIO GPIOB
#define HW_ICU_PIN 6 #define HW_ICU_PIN 6
// Measurement macros // Measurement macros
#define ADC_V_L1 ADC_Value[ADC_IND_SENS1] #define ADC_V_L1 ADC_Value[ADC_IND_SENS1]
#define ADC_V_L2 ADC_Value[ADC_IND_SENS2] #define ADC_V_L2 ADC_Value[ADC_IND_SENS2]
#define ADC_V_L3 ADC_Value[ADC_IND_SENS3] #define ADC_V_L3 ADC_Value[ADC_IND_SENS3]
#define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2) #define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2)
// Macros // Macros
#define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1) #define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1)
#define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2) #define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2)
#define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3) #define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3)
// Override dead time. See the stm32f4 reference manual for calculating this value. // Override dead time. See the stm32f4 reference manual for calculating this value.
#define HW_DEAD_TIME_NSEC 0.0 // FD6288Q has 200ns built in deadtime #define HW_DEAD_TIME_NSEC 0.0 // FD6288Q has 200ns built in deadtime
// Default setting overrides // Default setting overrides
#ifndef MCCONF_L_MIN_VOLTAGE #ifndef MCCONF_L_MIN_VOLTAGE
#define MCCONF_L_MIN_VOLTAGE 8.0 // Minimum input voltage #define MCCONF_L_MIN_VOLTAGE 8.0 // Minimum input voltage
#endif #endif
#ifndef MCCONF_L_MAX_VOLTAGE
#define MCCONF_L_MAX_VOLTAGE 55.0 // Maximum input voltage
#endif
#ifndef MCCONF_DEFAULT_MOTOR_TYPE #ifndef MCCONF_DEFAULT_MOTOR_TYPE
#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC #define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC
#endif #endif
#ifndef MCCONF_FOC_F_ZV #ifndef MCCONF_FOC_F_ZV
#define MCCONF_FOC_F_ZV 25000.0 // Switching frequency reduced to allow rise time of low side shunts #define MCCONF_FOC_F_ZV 25000.0 // Switching frequency reduced to allow rise time of low side shunts
#endif #endif
#define HW_LIM_FOC_CTRL_LOOP_FREQ 5000.0, 25000.0 //Limit to 50kHz max
#ifndef MCCONF_L_MAX_ABS_CURRENT #ifndef MCCONF_L_MAX_ABS_CURRENT
#define MCCONF_L_MAX_ABS_CURRENT 80.0 // The maximum absolute current above which a fault is generated #define MCCONF_L_MAX_ABS_CURRENT 50.0 // The maximum absolute current above which a fault is generated
#endif #endif
#ifndef MCCONF_FOC_SAMPLE_V0_V7 #ifndef MCCONF_FOC_SAMPLE_V0_V7
#define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts) #define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts)
#endif #endif
#ifndef MCCONF_L_CURRENT_MAX #ifndef MCCONF_L_CURRENT_MAX
#define MCCONF_L_CURRENT_MAX 20.0 // Current limit in Amperes (Upper) #define MCCONF_L_CURRENT_MAX 20.0 // Current limit in Amperes (Upper)
#endif #endif
#ifndef MCCONF_L_CURRENT_MIN #ifndef MCCONF_L_CURRENT_MIN
#define MCCONF_L_CURRENT_MIN -20.0 // Current limit in Amperes (Lower) #define MCCONF_L_CURRENT_MIN -20.0 // Current limit in Amperes (Lower)
#endif #endif
#ifndef MCCONF_L_IN_CURRENT_MAX #ifndef MCCONF_L_IN_CURRENT_MAX
#define MCCONF_L_IN_CURRENT_MAX 20.0 // Input current limit in Amperes (Upper) #define MCCONF_L_IN_CURRENT_MAX 20.0 // Input current limit in Amperes (Upper)
@ -253,28 +241,20 @@
#endif #endif
// Setting limits // Setting limits
#define HW_LIM_CURRENT -40.0, 40.0
#define HW_LIM_CURRENT_IN -30.0, 30.0
#define HW_LIM_CURRENT_ABS 0.0, 50.0
#define HW_LIM_ERPM -200e3, 200e3
#define HW_LIM_DUTY_MIN 0.0, 0.1
#define HW_LIM_DUTY_MAX 0.0, 0.98
#define HW_LIM_TEMP_FET -40.0, 100.0
#ifdef HW_A50S_12S #ifdef HW_A50S_12S
#define HW_NAME "A50S V2.1 12S" #define HW_LIM_VIN 4.0, 56.0
#define HW_LIM_CURRENT -40.0, 40.0 #define MCCONF_L_MAX_VOLTAGE 55 // Maximum input voltage
#define HW_LIM_CURRENT_IN -30.0, 30.0
#define HW_LIM_CURRENT_ABS 0.0, 80.0
#define HW_LIM_VIN 4.0, 56.0
#define HW_LIM_ERPM -200e3, 200e3
#define HW_LIM_DUTY_MIN 0.0, 0.1
#define HW_LIM_DUTY_MAX 0.0, 0.93 // Duty cycle limited to allow rise time of low side shunts
#define HW_LIM_TEMP_FET -40.0, 100.0
#elif defined (HW_A50S_6S) #elif defined (HW_A50S_6S)
#define HW_NAME "A50S V2.1 6S" #define HW_LIM_VIN 4.0, 28.0
#define HW_LIM_CURRENT -50.0, 50.0 #define MCCONF_L_MAX_VOLTAGE 26 // Maximum input voltage
#define HW_LIM_CURRENT_IN -30.0, 30.0
#define HW_LIM_CURRENT_ABS 0.0, 80.0
#define HW_LIM_VIN 4.0, 28.0
#define HW_LIM_ERPM -200e3, 200e3
#define HW_LIM_DUTY_MIN 0.0, 0.1
#define HW_LIM_DUTY_MAX 0.0, 0.93 // Duty cycle limited to allow rise time of low side shunts
#define HW_LIM_TEMP_FET -40.0, 100.0
#else #else
#error "Must define a hardware type" #error "Must define a hardware type"
#endif #endif

7
motor/mc_interface.c
View File

@ -489,6 +489,7 @@ const char* mc_interface_fault_to_string(mc_fault_code fault) {
case FAULT_CODE_ENCODER_MAGNET_TOO_STRONG: return "FAULT_CODE_ENCODER_MAGNET_TOO_STRONG"; case FAULT_CODE_ENCODER_MAGNET_TOO_STRONG: return "FAULT_CODE_ENCODER_MAGNET_TOO_STRONG";
case FAULT_CODE_PHASE_FILTER: return "FAULT_CODE_PHASE_FILTER"; case FAULT_CODE_PHASE_FILTER: return "FAULT_CODE_PHASE_FILTER";
case FAULT_CODE_ENCODER_FAULT: return "FAULT_CODE_ENCODER_FAULT"; case FAULT_CODE_ENCODER_FAULT: return "FAULT_CODE_ENCODER_FAULT";
case FAULT_CODE_LV_OUTPUT_FAULT: return "FAULT_CODE_LV_OUTPUT_FAULT";
} }
return "Unknown fault"; return "Unknown fault";
@ -1958,6 +1959,12 @@ void mc_interface_mc_timer_isr(bool is_second_motor) {
} }
#endif #endif
#ifdef HW_HAS_LV_OUTPUT_PROTECTION
if(IS_LV_OUTPUT_FAULT()) {
mc_interface_fault_stop(FAULT_CODE_LV_OUTPUT_FAULT, is_second_motor, true);
}
#endif
float t_samp = 1.0 / motor->m_f_samp_now; float t_samp = 1.0 / motor->m_f_samp_now;
// Watt and ah counters // Watt and ah counters

8
package_firmware.py
View File

@ -51,9 +51,13 @@ package_dict["HD60"] = [['hd60', default_name],
package_dict["HD75"] = [['hd75', default_name], package_dict["HD75"] = [['hd75', default_name],
['hd75_no_limits', no_limits_name]] ['hd75_no_limits', no_limits_name]]
package_dict["A50S_6S"] = [['a50s_6s', default_name]] package_dict["A50S_6S"] = [['a50s_6s', default_name]]
package_dict["A50S_6S_HG"] = [['a50s_6s_hg', default_name]]
package_dict["A50S_12S"] = [['a50s_12s', default_name]] package_dict["A50S_12S"] = [['a50s_12s', default_name]]
package_dict["A200S_v2.1"] = [['a200s_v2.1', default_name]] package_dict["A50S_12S_HG"] = [['a50s_12s_hg', default_name]]
package_dict["A200S_v2.2"] = [['a200s_v2.2', default_name]] package_dict["A200S_V2.1"] = [['a200s_v2.1', default_name]]
package_dict["A200S_V2.2"] = [['a200s_v2.2', default_name]]
package_dict["A200S_V3"] = [['a200s_v3', default_name]]
package_dict["A200S_V4"] = [['a200s_v4', default_name]]
package_dict["100_250"] = [['100_250', default_name], package_dict["100_250"] = [['100_250', default_name],
['100_250_no_limits', no_limits_name]] ['100_250_no_limits', no_limits_name]]
package_dict["LUNA_BBSHD"] = [['luna_bbshd', default_name]] package_dict["LUNA_BBSHD"] = [['luna_bbshd', default_name]]