From 1d08745376c14cb0ebff14b4322c82b9284b5f1e Mon Sep 17 00:00:00 2001 From: Marcos Chaparro Date: Sat, 20 Apr 2019 16:35:34 -0300 Subject: [PATCH] Axiom control board support Rename paltatech naming to Axiom. For safety set Axiom default max input voltage to 0.0V so it can not run a motor without mc_conf being explicitly configured by the user. Signed-off-by: Marcos Chaparro --- README.md | 4 +- build_all/{PALTA => AXIOM}/VESC_default.bin | Bin build_all/rebuild_all | 6 +- conf_general.h | 4 +- hwconf/{hw_palta.c => hw_axiom.c} | 76 +++++----- hwconf/{hw_palta.h => hw_axiom.h} | 142 +++++++++--------- ..._bitstream.c => hw_axiom_fpga_bitstream.c} | 0 mc_interface.c | 4 +- mcpwm_foc.c | 4 +- terminal.c | 4 +- virtual_motor.c | 2 +- 11 files changed, 128 insertions(+), 118 deletions(-) rename build_all/{PALTA => AXIOM}/VESC_default.bin (100%) rename hwconf/{hw_palta.c => hw_axiom.c} (89%) rename hwconf/{hw_palta.h => hw_axiom.h} (63%) rename hwconf/{hw_palta_fpga_bitstream.c => hw_axiom_fpga_bitstream.c} (100%) diff --git a/README.md b/README.md index 99b6d6fd..ef3df771 100644 --- a/README.md +++ b/README.md @@ -51,8 +51,8 @@ Make sure you select your board in [conf_general.h](conf_general.h) //#define HW_SOURCE "hw_das_rs.c" //#define HW_HEADER "hw_das_rs.h" -//#define HW_SOURCE "hw_palta.c" -//#define HW_HEADER "hw_palta.h" +//#define HW_SOURCE "hw_axiom.c" +//#define HW_HEADER "hw_axiom.h" //#define HW_SOURCE "hw_rh.c" //#define HW_HEADER "hw_rh.h" diff --git a/build_all/PALTA/VESC_default.bin b/build_all/AXIOM/VESC_default.bin similarity index 100% rename from build_all/PALTA/VESC_default.bin rename to build_all/AXIOM/VESC_default.bin diff --git a/build_all/rebuild_all b/build_all/rebuild_all index 8b5091b2..491414a5 100755 --- a/build_all/rebuild_all +++ b/build_all/rebuild_all @@ -255,15 +255,15 @@ cd $FWPATH make clean cd $DIR -#################### HW PALTA ######################## +#################### HW AXIOM ######################## -COPYDIR=PALTA +COPYDIR=AXIOM rm -f $COPYDIR/* # default cd $FWPATH touch conf_general.h -make -j8 build_args='-DHW_SOURCE=\"hw_palta.c\" -DHW_HEADER=\"hw_palta.h\"' USE_VERBOSE_COMPILE=no +make -j8 build_args='-DHW_SOURCE=\"hw_axiom.c\" -DHW_HEADER=\"hw_axiom.h\"' USE_VERBOSE_COMPILE=no cd $DIR cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default.bin diff --git a/conf_general.h b/conf_general.h index 0cdd7932..abe109d6 100644 --- a/conf_general.h +++ b/conf_general.h @@ -79,8 +79,8 @@ //#define HW_SOURCE "hw_das_rs.c" //#define HW_HEADER "hw_das_rs.h" -//#define HW_SOURCE "hw_palta.c" -//#define HW_HEADER "hw_palta.h" +//#define HW_SOURCE "hw_axiom.c" +//#define HW_HEADER "hw_axiom.h" //#define HW_SOURCE "hw_rh.c" //#define HW_HEADER "hw_rh.h" diff --git a/hwconf/hw_palta.c b/hwconf/hw_axiom.c similarity index 89% rename from hwconf/hw_palta.c rename to hwconf/hw_axiom.c index e1c24f29..21254b9d 100644 --- a/hwconf/hw_palta.c +++ b/hwconf/hw_axiom.c @@ -1,5 +1,10 @@ /* Copyright 2017 Benjamin Vedder benjamin@vedder.se + Copyright 2019 Marcos Chaparro mchaparro@powerdesigns.ca + + For support, please contact www.powerdesigns.ca + + This file is part of the VESC firmware. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -16,7 +21,6 @@ */ #include "hw.h" - #include "ch.h" #include "hal.h" #include "stm32f4xx_conf.h" @@ -25,7 +29,7 @@ #include "terminal.h" #include "commands.h" -#include "hw_palta_fpga_bitstream.c" //this file ONLY contains the fpga binary blob +#include "hw_axiom_fpga_bitstream.c" //this file ONLY contains the fpga binary blob // Defines #define SPI_SW_MISO_GPIO HW_SPI_PORT_MISO @@ -37,14 +41,14 @@ #define SPI_SW_FPGA_CS_GPIO GPIOB #define SPI_SW_FPGA_CS_PIN 7 -#define PALTA_FPGA_CLK_PORT GPIOC -#define PALTA_FPGA_CLK_PIN 9 -#define PALTA_FPGA_RESET_PORT GPIOB +#define AXIOM_FPGA_CLK_PORT GPIOC +#define AXIOM_FPGA_CLK_PIN 9 +#define AXIOM_FPGA_RESET_PORT GPIOB #ifdef HW_PALTA_REV_B -#define PALTA_FPGA_RESET_PIN 5 +#define AXIOM_FPGA_RESET_PIN 5 #else -#define PALTA_FPGA_RESET_PIN 4 +#define AXIOM_FPGA_RESET_PIN 4 #endif #define BITSTREAM_SIZE 104090 //ice40up5k @@ -68,19 +72,19 @@ static void spi_transfer(uint8_t *in_buf, const uint8_t *out_buf, int length); static void spi_begin(void); static void spi_end(void); static void spi_delay(void); -void hw_palta_init_FPGA_CLK(void); -void hw_palta_setup_dac(void); -void hw_palta_configure_brownout(uint8_t); -void hw_palta_configure_VDD_undervoltage(void); +void hw_axiom_init_FPGA_CLK(void); +void hw_axiom_setup_dac(void); +void hw_axiom_configure_brownout(uint8_t); +void hw_axiom_configure_VDD_undervoltage(void); void hw_init_gpio(void) { // Set Brown out to keep mcu under reset until VDD reaches 2.7V - hw_palta_configure_brownout(OB_BOR_LEVEL3); + hw_axiom_configure_brownout(OB_BOR_LEVEL3); // Configure Programmable voltage detector to interrupt the cpu // when VDD is below 2.9V. - hw_palta_configure_VDD_undervoltage(); + hw_axiom_configure_VDD_undervoltage(); // GPIO clock enable RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); @@ -113,13 +117,13 @@ void hw_init_gpio(void) { palClearPad(SPI_SW_FPGA_CS_GPIO, SPI_SW_FPGA_CS_PIN); // FPGA RESET - palSetPadMode(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); - palClearPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN); + palSetPadMode(AXIOM_FPGA_RESET_PORT, AXIOM_FPGA_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); + palClearPad(AXIOM_FPGA_RESET_PORT, AXIOM_FPGA_RESET_PIN); chThdSleep(1); - palSetPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN); + palSetPad(AXIOM_FPGA_RESET_PORT, AXIOM_FPGA_RESET_PIN); //output a 12MHz clock on MCO2 - hw_palta_init_FPGA_CLK(); + hw_axiom_init_FPGA_CLK(); // GPIOA Configuration: Channel 1 to 3 as alternate function push-pull palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | @@ -156,8 +160,8 @@ void hw_init_gpio(void) { palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG); palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG); -#ifdef PALTA_USE_DAC - hw_palta_setup_dac(); +#ifdef HW_AXIOM_USE_DAC + hw_axiom_setup_dac(); #else palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG); //Temperature bridge A palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG); //Temperature bridge B @@ -178,13 +182,13 @@ void hw_init_gpio(void) { // Register terminal callbacks terminal_register_command_callback( - "palta_reset_oc", - "Reset latched overcurrent fault.", + "axiom_clear_faults", + "Reset latched FPGA faults.", 0, terminal_cmd_reset_oc); // Send bitstream over SPI to configure FPGA - hw_palta_configure_FPGA(); + hw_axiom_configure_FPGA(); } void hw_setup_adc_channels(void) { @@ -222,7 +226,7 @@ void hw_setup_adc_channels(void) { ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles); } -void hw_palta_setup_dac(void) { +void hw_axiom_setup_dac(void) { // GPIOA clock enable RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); @@ -237,19 +241,19 @@ void hw_palta_setup_dac(void) { DAC->CR |= DAC_CR_EN1 | DAC_CR_BOFF1 | DAC_CR_EN2 | DAC_CR_BOFF2; // Set DAC channels at 1.65V - hw_palta_DAC1_setdata(0x800); - hw_palta_DAC2_setdata(0x800); + hw_axiom_DAC1_setdata(0x800); + hw_axiom_DAC2_setdata(0x800); } -void hw_palta_DAC1_setdata(uint16_t data) { +void hw_axiom_DAC1_setdata(uint16_t data) { DAC->DHR12R1 = data; } -void hw_palta_DAC2_setdata(uint16_t data) { +void hw_axiom_DAC2_setdata(uint16_t data) { DAC->DHR12R2 = data; } -void hw_palta_configure_brownout(uint8_t BOR_level) { +void hw_axiom_configure_brownout(uint8_t BOR_level) { /* Get BOR Option Bytes */ if((FLASH_OB_GetBOR() & 0x0C) != BOR_level) { @@ -267,7 +271,7 @@ void hw_palta_configure_brownout(uint8_t BOR_level) { } } -void hw_palta_configure_VDD_undervoltage(void) { +void hw_axiom_configure_VDD_undervoltage(void) { // partially configured in mcuconf.h -> STM32_PVD_ENABLE and STM32_PLS @@ -383,8 +387,8 @@ static void terminal_cmd_reset_oc(int argc, const char **argv) { (void)argc; (void)argv; - hw_palta_configure_FPGA(); - commands_printf("Palta OC latch reset done!"); + hw_axiom_configure_FPGA(); + commands_printf("Axiom FPGA fault latch reset done!"); commands_printf(" "); } @@ -426,7 +430,7 @@ static void spi_transfer(uint8_t *in_buf, const uint8_t *out_buf, int length) { } } -void hw_palta_init_FPGA_CLK(void) { +void hw_axiom_init_FPGA_CLK(void) { /* Configure PLLI2S prescalers */ /* PLLI2S_VCO : VCO_192M */ /* SAI_CLK(first level) = PLLI2S_VCO/PLLI2SQ = 192/4 = 48 Mhz */ @@ -440,7 +444,7 @@ void hw_palta_init_FPGA_CLK(void) { } /* Configure MCO2 pin(PC9) in alternate function */ - palSetPadMode(PALTA_FPGA_CLK_PORT, PALTA_FPGA_CLK_PIN, PAL_MODE_ALTERNATE(GPIO_AF_MCO) | + palSetPadMode(AXIOM_FPGA_CLK_PORT, AXIOM_FPGA_CLK_PIN, PAL_MODE_ALTERNATE(GPIO_AF_MCO) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUDR_PULLUP); @@ -449,12 +453,12 @@ void hw_palta_init_FPGA_CLK(void) { RCC_MCO2Config(RCC_MCO2Source_PLLI2SCLK, RCC_MCO2Div_4); } -char hw_palta_configure_FPGA(void) { +char hw_axiom_configure_FPGA(void) { spi_begin(); palSetPad(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN); - palClearPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN); + palClearPad(AXIOM_FPGA_RESET_PORT, AXIOM_FPGA_RESET_PIN); chThdSleep(10); - palSetPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN); + palSetPad(AXIOM_FPGA_RESET_PORT, AXIOM_FPGA_RESET_PIN); chThdSleep(20); spi_transfer(0, FPGA_bitstream, BITSTREAM_SIZE); diff --git a/hwconf/hw_palta.h b/hwconf/hw_axiom.h similarity index 63% rename from hwconf/hw_palta.h rename to hwconf/hw_axiom.h index 57227087..1e6a4e7e 100644 --- a/hwconf/hw_palta.h +++ b/hwconf/hw_axiom.h @@ -1,5 +1,8 @@ /* Copyright 2017 Benjamin Vedder benjamin@vedder.se + Copyright 2019 Marcos Chaparro mchaparro@powerdesigns.ca + + For support, please contact www.powerdesigns.ca This file is part of the VESC firmware. @@ -17,18 +20,16 @@ along with this program. If not, see . */ -#ifndef HW_PALTA_H_ -#define HW_PALTA_H_ +#ifndef HW_AXIOM_H_ +#define HW_AXIOM_H_ -#define HW_NAME "PALTA" +#define HW_NAME "AXIOM" -#define PALTA_USE_DAC -//#define PALTA_USE_MOTOR_TEMP -#define HW_PALTA_USE_LINE_TO_LINE -#define HW_PALTA_FORCE_HIGH_CURRENT_MEASUREMENTS -#define HW_VERSION_PALTA - -//#define HW_PALTA_REV_B +#define HW_AXIOM_USE_DAC +//#define HW_AXIOM_USE_MOTOR_TEMP +#define HW_USE_LINE_TO_LINE +#define HW_AXIOM_FORCE_HIGH_CURRENT_MEASUREMENTS +#define HW_VERSION_AXIOM // HW properties #define HW_HAS_3_SHUNTS @@ -73,73 +74,77 @@ * 14: IN1 SENS2 */ -#define HW_ADC_CHANNELS 15 -#define HW_ADC_INJ_CHANNELS 3 -#define HW_ADC_NBR_CONV 5 +#define HW_ADC_CHANNELS 15 +#define HW_ADC_INJ_CHANNELS 3 +#define HW_ADC_NBR_CONV 5 // ADC Indexes -#define ADC_IND_SENS1 0 -#define ADC_IND_SENS2 1 -#define ADC_IND_SENS3 2 -#define ADC_IND_CURR1 3 -#define ADC_IND_CURR2 4 -#define ADC_IND_CURR3 5 -#define ADC_IND_VIN_SENS 11 -#define ADC_IND_VOUT_GATE_DRV 12 -#define ADC_IND_EXT 10 -#define ADC_IND_EXT2 6 -#define ADC_IND_TEMP_MOS 8 -#define ADC_IND_TEMP_MOTOR 9 -//#define ADC_IND_VREFINT 12 +#define ADC_IND_SENS1 0 +#define ADC_IND_SENS2 1 +#define ADC_IND_SENS3 2 +#define ADC_IND_CURR1 3 +#define ADC_IND_CURR2 4 +#define ADC_IND_CURR3 5 +#define ADC_IND_VIN_SENS 11 +#define ADC_IND_VOUT_GATE_DRV 12 +#define ADC_IND_EXT 10 +#define ADC_IND_EXT2 6 +#define ADC_IND_TEMP_MOS 8 +#define ADC_IND_TEMP_MOTOR 9 // ADC macros and settings +#ifdef HW_PALTA_REV_B +#define HVDC_TRANSFER_FUNCTION 112.15 //[V/V] +#define PHASE_TRANSFER_FUNCTION 112.15 //[V/V] +#else +#define HVDC_TRANSFER_FUNCTION 185.0 //[V/V] +#define PHASE_VOLTAGE_TRANSFER_FUNCTION 185.0 //[V/V] +#endif + // Component parameters (can be overridden) #ifndef V_REG -#define V_REG 3.3 +#define V_REG 3.3 #endif #ifndef VIN_R1 -#ifdef HW_PALTA_REV_B -#define VIN_R1 112.15 //TF since RevC = 113.15V/V -#else -#define VIN_R1 184.0 //TF since RevC = 185V/V -#endif +#define VIN_R1 (PHASE_VOLTAGE_TRANSFER_FUNCTION - 1.0) #endif #ifndef VIN_R2 -#define VIN_R2 1.0 +#define VIN_R2 1.0 #endif #ifndef CURRENT_AMP_GAIN -#define CURRENT_AMP_GAIN 0.003761 //Transfer Function [V/A] for ISB-425-A -//#define CURRENT_AMP_GAIN 0.001249 //Transfer Function [V/A] for HTFS 800-P +#define CURRENT_AMP_GAIN 0.003761 //Transfer Function [V/A] for ISB-425-A +//#define CURRENT_AMP_GAIN 0.001249 //Transfer Function [V/A] for HTFS 800-P +//#define CURRENT_AMP_GAIN 0.0008324 //Transfer Function [V/A] for HASS 600-S #endif #ifndef CURRENT_SHUNT_RES -#define CURRENT_SHUNT_RES 1.000 // Unity gain so we use a single transfer function defined as CURRENT_AMP_GAIN +#define CURRENT_SHUNT_RES 1.0 // Unity gain so we use a single transfer function defined as CURRENT_AMP_GAIN #endif -#define HW_MAX_CURRENT_OFFSET 620 // More than this offset (0.5 Vdc) trips the offset fault (likely a sensor disconnected) -#define MCCONF_MAX_CURRENT_UNBALANCE 130.0 // [Amp] More than this unbalance trips the fault (likely a sensor disconnected) -#define MCCONF_MAX_CURRENT_UNBALANCE_RATE 0.3 // Fault if more than 30% of the time the motor is unbalanced +#define HW_MAX_CURRENT_OFFSET 620 // More than this offset (0.5 Vdc) trips the offset fault (likely a sensor disconnected) +#define MCCONF_MAX_CURRENT_UNBALANCE 130.0 // [Amp] More than this unbalance trips the fault (likely a sensor disconnected) +#define MCCONF_MAX_CURRENT_UNBALANCE_RATE 0.3 // Fault if more than 30% of the time the motor is unbalanced // Input voltage -#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2)) +#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * (HVDC_TRANSFER_FUNCTION)) // NTC Termistors -#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0) -#define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3434.0) + (1.0 / 298.15)) - 273.15) +#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0) +#define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3434.0) + (1.0 / 298.15)) - 273.15) -#define NTC_RES_MOTOR(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0) +#define NTC_RES_MOTOR(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0) -#ifdef PALTA_USE_MOTOR_TEMP -#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15) +#ifdef HW_AXIOM_USE_MOTOR_TEMP +#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15) #else -#define NTC_TEMP_MOTOR(beta) 25.0 +#define NTC_TEMP_MOTOR(beta) 25.0 #endif // Voltage on ADC channel -#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG) +#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG) // Sin/Cos Encoder signals -#define ENCODER_SIN_VOLTS ADC_VOLTS(ADC_IND_EXT) -#define ENCODER_COS_VOLTS ADC_VOLTS(ADC_IND_EXT2) +#define ENCODER_SIN_VOLTS ADC_VOLTS(ADC_IND_EXT) +#define ENCODER_COS_VOLTS ADC_VOLTS(ADC_IND_EXT2) #ifdef HW_PALTA_REV_B #define GET_GATE_DRIVER_SUPPLY_VOLTAGE() 15.0 @@ -148,9 +153,7 @@ #define GET_GATE_DRIVER_SUPPLY_VOLTAGE() ((float)ADC_VOLTS(ADC_IND_VOUT_GATE_DRV) * 11.0) #endif -#define ANGLE_TO_DAC_VALUE(angle) ( angle * 512.0 + 0x800 )//angle between -pi to pi -#define CURRENT_TO_DAC_VALUE(current) ( current * 70.0 + 0x800 )//current -#define VOLTAGE_TO_DAC_VALUE(voltage) ( voltage * 40.0 + 0x800 )//angle between -pi to pi +#define ANGLE_TO_DAC_VALUE(angle) ( angle * 512.0 + 0x800 )//angle between -pi to pi // Double samples in beginning and end for positive current measurement. // Useful when the shunt sense traces have noise that causes offset. @@ -240,7 +243,7 @@ #define ADC_V_L1 (ADC_Value[ADC_IND_SENS1]-2048) //phase voltages are centered in 1.65V #define ADC_V_L2 (ADC_Value[ADC_IND_SENS2]-2048) #define ADC_V_L3 (ADC_Value[ADC_IND_SENS3]-2048) -#define ADC_V_ZERO 0 //(ADC_Value[ADC_IND_VIN_SENS] / 2) +#define ADC_V_ZERO 0 // Macros #define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1) @@ -248,7 +251,7 @@ #define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3) // Override dead time. See the stm32f4 reference manual for calculating this value. -#define HW_DEAD_TIME_NSEC 1400.0 +#define HW_DEAD_TIME_NSEC 1400.0 #define HW_GATE_DRIVER_SUPPLY_MAX_VOLTAGE 16.0 #define HW_GATE_DRIVER_SUPPLY_MIN_VOLTAGE 14.0 @@ -261,24 +264,27 @@ #define MCCONF_FOC_SAMPLE_V0_V7 true // Run control loop in both v0 and v7 (requires phase shunts) #endif +#ifndef MCCONF_L_MAX_VOLTAGE +#define MCCONF_L_MAX_VOLTAGE 0.0 // For safety the board will be held in fault until mc_conf is configured by the user +#endif + // Execute FOC loop once every "FOC_CONTROL_LOOP_FREQ_DIVIDER" ADC ISR calls #define FOC_CONTROL_LOOP_FREQ_DIVIDER 1 // Setting limits -#define HW_LIM_CURRENT -200.0, 200.0 -#define HW_LIM_CURRENT_IN -100.0, 100.0 -#define HW_LIM_CURRENT_ABS 0.0, 230.0 -#define HW_LIM_VIN 6.0, 400.0 -#define HW_LIM_ERPM -100e3, 100e3 -#define HW_LIM_DUTY_MIN 0.0, 0.1 -#define HW_LIM_DUTY_MAX 0.0, 1.0 -#define HW_LIM_TEMP_FET -40.0, 110.0 -#define HW_LIM_FOC_CTRL_LOOP_FREQ 10000.0, 30000.0 //at around 38kHz the RTOS starts crashing (26us FOC ISR) - +#define HW_LIM_CURRENT -425.0, 425.0 +#define HW_LIM_CURRENT_IN -400.0, 400.0 +#define HW_LIM_CURRENT_ABS 0.0, 400.0 +#define HW_LIM_VIN 0.0, 420.0 +#define HW_LIM_ERPM -100e3, 100e3 +#define HW_LIM_DUTY_MIN 0.0, 0.1 +#define HW_LIM_DUTY_MAX 0.0, 1.0 +#define HW_LIM_TEMP_FET -40.0, 110.0 +#define HW_LIM_FOC_CTRL_LOOP_FREQ 5000.0, 30000.0 //at around 38kHz the RTOS starts crashing (26us FOC ISR) // HW-specific functions -char hw_palta_configure_FPGA(void); -void hw_palta_DAC1_setdata(uint16_t data); -void hw_palta_DAC2_setdata(uint16_t data); +char hw_axiom_configure_FPGA(void); +void hw_axiom_DAC1_setdata(uint16_t data); +void hw_axiom_DAC2_setdata(uint16_t data); -#endif /* HW_PALTA_H_ */ +#endif /* HW_AXIOM_H_ */ diff --git a/hwconf/hw_palta_fpga_bitstream.c b/hwconf/hw_axiom_fpga_bitstream.c similarity index 100% rename from hwconf/hw_palta_fpga_bitstream.c rename to hwconf/hw_axiom_fpga_bitstream.c diff --git a/mc_interface.c b/mc_interface.c index a0c44d8e..cef0bd65 100644 --- a/mc_interface.c +++ b/mc_interface.c @@ -1371,7 +1371,7 @@ void mc_interface_mc_timer_isr(void) { mc_interface_fault_stop(FAULT_CODE_DRV); } -#ifdef HW_VERSION_PALTA +#ifdef HW_VERSION_AXIOM if( m_gate_driver_voltage > HW_GATE_DRIVER_SUPPLY_MAX_VOLTAGE) { mc_interface_fault_stop(FAULT_CODE_GATE_DRIVER_OVER_VOLTAGE); } @@ -1576,7 +1576,7 @@ static void update_override_limits(volatile mc_configuration *conf) { UTILS_LP_FAST(m_temp_fet, NTC_TEMP(ADC_IND_TEMP_MOS), 0.1); UTILS_LP_FAST(m_temp_motor, NTC_TEMP_MOTOR(conf->m_ntc_motor_beta), 0.1); -#ifdef HW_VERSION_PALTA +#ifdef HW_VERSION_AXIOM UTILS_LP_FAST(m_gate_driver_voltage, GET_GATE_DRIVER_SUPPLY_VOLTAGE(), 0.01); #endif diff --git a/mcpwm_foc.c b/mcpwm_foc.c index d53afc57..1c84b54d 100644 --- a/mcpwm_foc.c +++ b/mcpwm_foc.c @@ -1509,7 +1509,7 @@ bool mcpwm_foc_measure_res_ind(float *res, float *ind) { i_last = (m_conf->l_current_max / 2.0); } -#ifdef HW_PALTA_FORCE_HIGH_CURRENT_MEASUREMENTS +#ifdef HW_AXIOM_FORCE_HIGH_CURRENT_MEASUREMENTS i_last = (m_conf->l_current_max / 2.0); #endif @@ -2064,7 +2064,7 @@ void mcpwm_foc_adc_int_handler(void *p, uint32_t flags) { float c, s; utils_fast_sincos_better(m_motor_state.phase, &s, &c); -#ifdef HW_PALTA_USE_LINE_TO_LINE +#ifdef HW_USE_LINE_TO_LINE // rotate alpha-beta 30 degrees to compensate for line-to-line phase voltage sensing float x_tmp = m_motor_state.v_alpha; float y_tmp = m_motor_state.v_beta; diff --git a/terminal.c b/terminal.c index c02f8cbb..89e45856 100644 --- a/terminal.c +++ b/terminal.c @@ -122,7 +122,7 @@ void terminal_process_string(char *str) { commands_printf("Current : %.1f", (double)fault_vec[i].current); commands_printf("Current filtered : %.1f", (double)fault_vec[i].current_filtered); commands_printf("Voltage : %.2f", (double)fault_vec[i].voltage); -#ifdef HW_VERSION_PALTA +#ifdef HW_VERSION_AXIOM commands_printf("Gate drv voltage : %.2f", (double)fault_vec[i].gate_driver_voltage); #endif commands_printf("Duty : %.3f", (double)fault_vec[i].duty); @@ -182,7 +182,7 @@ void terminal_process_string(char *str) { commands_printf("Current 2 sample: %u\n", current2_samp); } else if (strcmp(argv[0], "volt") == 0) { commands_printf("Input voltage: %.2f\n", (double)GET_INPUT_VOLTAGE()); -#ifdef HW_VERSION_PALTA +#ifdef HW_VERSION_AXIOM commands_printf("Gate driver power supply output voltage: %.2f\n", (double)GET_GATE_DRIVER_SUPPLY_VOLTAGE()); #endif } else if (strcmp(argv[0], "param_detect") == 0) { diff --git a/virtual_motor.c b/virtual_motor.c index ec4c7311..2e9a21a6 100644 --- a/virtual_motor.c +++ b/virtual_motor.c @@ -180,7 +180,7 @@ static void connect_virtual_motor(float ml , float J, float Ld, float Lq, ADC_Value[ ADC_IND_VIN_SENS ] = Vbus * VOLTAGE_TO_ADC_FACTOR; ADC_Value[ ADC_IND_TEMP_MOS ] = 2048; ADC_Value[ ADC_IND_TEMP_MOTOR ] = 2048; -#ifdef HW_VERSION_PALTA +#ifdef HW_VERSION_AXIOM ADC_Value[ ADC_IND_VOUT_GATE_DRV ] = 1692; // 1692 gives 15.0 as Gate Driver Voltage //( 15.0 = (ADC_Value[] * 11.0 * 3.3) / 4096 )