mirror of https://github.com/rusefi/bldc.git
Add FPGA configuration on boot
Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
This commit is contained in:
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0827837e5f
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@ -28,11 +28,26 @@
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#include "commands.h"
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// Defines
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#define SPI_SW_MISO_GPIO HW_SPI_PORT_MISO
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#define SPI_SW_MISO_PIN HW_SPI_PIN_MISO
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#define SPI_SW_MOSI_GPIO HW_SPI_PORT_MOSI
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#define SPI_SW_MOSI_PIN HW_SPI_PIN_MOSI
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#define SPI_SW_SCK_GPIO HW_SPI_PORT_SCK
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#define SPI_SW_SCK_PIN HW_SPI_PIN_SCK
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#define SPI_SW_FPGA_CS_GPIO GPIOB
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#define SPI_SW_FPGA_CS_PIN 7
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#define PALTA_FPGA_CLK_PORT GPIOC
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#define PALTA_FPGA_CLK_PIN 9
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#define PALTA_FPGA_RESET_PORT GPIOB
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#define PALTA_FPGA_RESET_PIN 4
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//#define BITSTREAM_SIZE 104090 //ice40up5k
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#define BITSTREAM_SIZE 71338 //ice40LP1K
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// Variables
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static volatile bool i2c_running = false;
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extern unsigned char FPGA_bitstream[BITSTREAM_SIZE];
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// I2C configuration
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static const I2CConfig i2cfg = {
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@ -43,6 +58,10 @@ static const I2CConfig i2cfg = {
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// Private functions
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static void terminal_cmd_reset_oc(int argc, const char **argv);
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static void spi_transfer(uint8_t *in_buf, const uint8_t *out_buf, int length);
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static void spi_begin(void);
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static void spi_end(void);
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static void spi_delay(void);
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void hw_palta_init_FPGA_CLK(void);
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void hw_palta_setup_dac(void);
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@ -68,12 +87,20 @@ void hw_init_gpio(void) {
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ENABLE_GATE();
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// OC latch
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palSetPadMode(PALTA_OC_CLR_PORT, PALTA_OC_CLR_PIN,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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// FPGA SPI port
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palSetPadMode(SPI_SW_MISO_GPIO, SPI_SW_MISO_PIN, PAL_MODE_INPUT);
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palSetPadMode(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SPI_SW_FPGA_CS_GPIO, SPI_SW_FPGA_CS_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SPI_SW_MOSI_GPIO, SPI_SW_MOSI_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
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hw_palta_reset_oc();
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// Set FPGA SS to '0' to make it start in slave mode
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palClearPad(SPI_SW_FPGA_CS_GPIO, SPI_SW_FPGA_CS_PIN);
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// FPGA RESET
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palSetPadMode(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
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palClearPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN);
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chThdSleep(1);
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palSetPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN);
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//output a 12MHz clock on MCO2
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hw_palta_init_FPGA_CLK();
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@ -137,6 +164,9 @@ void hw_init_gpio(void) {
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"Reset latched overcurrent fault.",
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0,
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terminal_cmd_reset_oc);
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// Send bitstream over SPI to configure FPGA
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hw_palta_configure_FPGA();
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}
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void hw_setup_adc_channels(void) {
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@ -316,11 +346,49 @@ static void terminal_cmd_reset_oc(int argc, const char **argv) {
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(void)argc;
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(void)argv;
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hw_palta_reset_oc();
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hw_palta_configure_FPGA();
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commands_printf("Palta OC latch reset done!");
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commands_printf(" ");
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}
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// Software SPI for FPGA control
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static void spi_transfer(uint8_t *in_buf, const uint8_t *out_buf, int length) {
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for (int i = 0;i < length;i++) {
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uint8_t send = out_buf ? out_buf[i] : 0xFF;
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uint8_t recieve = 0;
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for (int bit = 0;bit < 8;bit++) {
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palWritePad(HW_SPI_PORT_MOSI, HW_SPI_PIN_MOSI, send >> 7);
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send <<= 1;
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spi_delay();
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palSetPad(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN);
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spi_delay();
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/*
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int r1, r2, r3;
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r1 = palReadPad(SPI_SW_MISO_GPIO, SPI_SW_MISO_PIN);
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__NOP();
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r2 = palReadPad(SPI_SW_MISO_GPIO, SPI_SW_MISO_PIN);
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__NOP();
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r3 = palReadPad(SPI_SW_MISO_GPIO, SPI_SW_MISO_PIN);
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recieve <<= 1;
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if (utils_middle_of_3_int(r1, r2, r3)) {
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recieve |= 1;
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}
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*/
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palClearPad(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN);
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spi_delay();
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}
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if (in_buf) {
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in_buf[i] = recieve;
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}
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}
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}
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void hw_palta_init_FPGA_CLK(void) {
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/* Configure PLLI2S prescalers */
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/* PLLI2S_VCO : VCO_192M */
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@ -344,4 +412,43 @@ void hw_palta_init_FPGA_CLK(void) {
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RCC_MCO2Config(RCC_MCO2Source_PLLI2SCLK, RCC_MCO2Div_4);
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}
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char hw_palta_configure_FPGA(void) {
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spi_begin();
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palSetPad(SPI_SW_SCK_GPIO, SPI_SW_SCK_PIN);
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palClearPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN);
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chThdSleep(10);
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palSetPad(PALTA_FPGA_RESET_PORT, PALTA_FPGA_RESET_PIN);
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chThdSleep(20);
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spi_transfer(0, FPGA_bitstream, BITSTREAM_SIZE);
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//include 49 extra spi clock cycles, dummy bytes
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uint8_t dummy = 0;
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spi_transfer(0, &dummy, 7);
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spi_end();
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// CDONE LED should be set by now
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return 0;
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}
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static void spi_begin(void) {
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palClearPad(SPI_SW_FPGA_CS_GPIO, SPI_SW_FPGA_CS_PIN);
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}
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static void spi_end(void) {
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palSetPad(SPI_SW_FPGA_CS_GPIO, SPI_SW_FPGA_CS_PIN);
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}
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static void spi_delay(void) {
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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}
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#endif
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@ -226,7 +226,7 @@
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//#define HW_LIM_TEMP_FET -40.0, 110.0
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// HW-specific functions
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void hw_palta_reset_oc(void);
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char hw_palta_configure_FPGA(void);
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void hw_palta_DAC1_setdata(uint16_t data);
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void hw_palta_DAC2_setdata(uint16_t data);
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@ -0,0 +1 @@
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const unsigned char FPGA_bitstream[71338] = {0};
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@ -11,6 +11,7 @@ HWSRC = hwconf/hw_40.c \
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hwconf/drv8301.c \
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hwconf/drv8305.c \
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hwconf/drv8320.c \
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hwconf/hw_palta_fpga_bitstream.c \
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hwconf/hw_palta.c \
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hwconf/hw_rh.c \
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hwconf/hw_tp.c \
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