rusefi
/
bldc
mirror of https://github.com/rusefi/bldc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixing spelling errors in comments. 

Adjusting whitespace to adhere to coding style.
This commit is contained in:
Zach O'Brien 2022-07-19 09:35:38 -06:00
parent 86c1cdad92
commit 93e74e5363
3 changed files with 8 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
encoder/enc_as5x47u.c
View File

@ -56,10 +56,10 @@
#define AS5x47U_SPI_POS_ADR 0x3FFF
#define AS5x47U_SPI_READ_ERRFL_MSG (AS5x47U_SPI_ERRFL_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_DIAG_MSG (AS5x47U_SPI_DIAG_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_MAGN_MSG (AS5x47U_SPI_MAGN_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_AGC_MSG (AS5x47U_SPI_AGC_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_POS_MSG (AS5x47U_SPI_POS_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_DIAG_MSG (AS5x47U_SPI_DIAG_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_MAGN_MSG (AS5x47U_SPI_MAGN_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_AGC_MSG (AS5x47U_SPI_AGC_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_POS_MSG (AS5x47U_SPI_POS_ADR | AS5x47U_SPI_READ_BIT)
#define AS5x47U_SPI_READ_ERRFL_CRC (0x06)
#define AS5x47U_SPI_READ_DIAG_CRC (0x6F)
@ -83,7 +83,6 @@ enum {
// Private functions
static void AS5x47U_determinate_if_connected(AS5x47U_config_t *cfg, bool was_last_valid);
// static void AS5x47U_start_spi_exchange(AS5x47U_config_t *cfg, uint16_t tx_data);
static void AS5x47U_start_spi_exchange_precalc_crc(AS5x47U_config_t *cfg,
uint16_t tx_data, uint8_t tx_crc);
static void AS5x47U_process_pos(AS5x47U_config_t *cfg, uint16_t posData);
@ -365,7 +364,7 @@ static void AS5x47U_start_spi_exchange_precalc_crc(AS5x47U_config_t *cfg,
memset(cfg->state.rx_buf, 0, sizeof(cfg->state.rx_buf));
// There is a weird corner case where the DMA may not read all of the Rx data. This
// causes the RXNE flag to be set when an exchange starts, causing the fist byte of
// causes the RXNE flag to be set when an exchange starts, causing the first byte of
// data received to be from the previous exchange. This is corrected by reading the
// SPI data register, clearing the RXNE flag.
volatile uint32_t test = cfg->spi_dev->spi->DR;

2
encoder/enc_as5x47u.h
View File

@ -37,7 +37,7 @@ void enc_as5x47u_deinit(AS5x47U_config_t *cfg);
/**
* @brief Starts a new SPI transaction to get the current position from the position sensor.
*
* Every call of enc_as5x47u_routine ends up doing two SPI trnasactions. The first one
* Every call of enc_as5x47u_routine ends up doing two SPI transactions. The first one
* always receives position, but will request one of MAGN, AGC, DIAG, or ERRFL. The next
* transaction receives the requested register while requesting pos for the next
* transaction.

4
encoder/encoder.c
View File

@ -341,9 +341,9 @@ void encoder_check_faults(volatile mc_configuration *m_conf, bool is_second_moto
if (diag.is_Comp_high) {
mc_interface_fault_stop(FAULT_CODE_ENCODER_NO_MAGNET, is_second_motor, false);
} else if(diag.is_Comp_low) {
} else if (diag.is_Comp_low) {
mc_interface_fault_stop(FAULT_CODE_ENCODER_MAGNET_TOO_STRONG, is_second_motor, false);
} else if(diag.is_broken_hall || diag.is_COF || diag.is_wdtst) {
} else if (diag.is_broken_hall || diag.is_COF || diag.is_wdtst) {
mc_interface_fault_stop(FAULT_CODE_ENCODER_FAULT, is_second_motor, false);
}