From b7d9a72878addf0da27266adba5b9e75463d0421 Mon Sep 17 00:00:00 2001 From: Benjamin Vedder Date: Wed, 12 Jun 2024 23:18:46 +0200 Subject: [PATCH] Added hw_basic --- hwconf/vesc/basic/hw_basic.h | 27 +++ hwconf/vesc/basic/hw_basic_core.c | 304 ++++++++++++++++++++++++++++++ hwconf/vesc/basic/hw_basic_core.h | 265 ++++++++++++++++++++++++++ package_firmware.py | 2 + 4 files changed, 598 insertions(+) create mode 100644 hwconf/vesc/basic/hw_basic.h create mode 100644 hwconf/vesc/basic/hw_basic_core.c create mode 100644 hwconf/vesc/basic/hw_basic_core.h diff --git a/hwconf/vesc/basic/hw_basic.h b/hwconf/vesc/basic/hw_basic.h new file mode 100644 index 00000000..157d7f5d --- /dev/null +++ b/hwconf/vesc/basic/hw_basic.h @@ -0,0 +1,27 @@ +/* + Copyright 2018 Benjamin Vedder benjamin@vedder.se + + This file is part of the VESC firmware. + + The VESC firmware is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + The VESC firmware is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + */ + +#ifndef HW_BASIC_H_ +#define HW_BASIC_H_ + +#define HW_BASIC + +#include "hw_basic_core.h" + +#endif /* HW_BASIC_H_ */ diff --git a/hwconf/vesc/basic/hw_basic_core.c b/hwconf/vesc/basic/hw_basic_core.c new file mode 100644 index 00000000..5c2c334b --- /dev/null +++ b/hwconf/vesc/basic/hw_basic_core.c @@ -0,0 +1,304 @@ +/* + Copyright 2023 Benjamin Vedder benjamin@vedder.se + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + */ + +#include "hw.h" + +#include "ch.h" +#include "hal.h" +#include "stm32f4xx_conf.h" +#include "utils_math.h" +#include +#include "mc_interface.h" +#include "lispif.h" +#include "lispbm.h" + +// Variables +static volatile bool i2c_running = false; + +// I2C configuration +static const I2CConfig i2cfg = { + OPMODE_I2C, + 100000, + STD_DUTY_CYCLE +}; + +static lbm_value ext_basic_read_brake(lbm_value *args, lbm_uint argn) { + (void)args; (void)argn; + + return lbm_enc_i(ADC_VOLTS(ADC_IND_EXT2) < 0.5 ? 1 : 0); +} + +static lbm_value ext_basic_set_out1(lbm_value *args, lbm_uint argn) { + LBM_CHECK_ARGN_NUMBER(1); + + if (lbm_dec_as_i32(args[0])) { + OUT_1_ON(); + } else { + OUT_1_OFF(); + } + + return ENC_SYM_TRUE; +} + +static lbm_value ext_basic_set_out2(lbm_value *args, lbm_uint argn) { + LBM_CHECK_ARGN_NUMBER(1); + + if (lbm_dec_as_i32(args[0])) { + OUT_2_ON(); + } else { + OUT_2_OFF(); + } + + return ENC_SYM_TRUE; +} + +static lbm_value ext_basic_set_out3(lbm_value *args, lbm_uint argn) { + LBM_CHECK_ARGN_NUMBER(1); + + if (lbm_dec_as_i32(args[0])) { + OUT_3_ON(); + } else { + OUT_3_OFF(); + } + + return ENC_SYM_TRUE; +} + +static void load_extensions(void) { + lbm_add_extension("basic-read-brake", ext_basic_read_brake); + lbm_add_extension("basic-set-out1", ext_basic_set_out1); + lbm_add_extension("basic-set-out2", ext_basic_set_out2); + lbm_add_extension("basic-set-out3", ext_basic_set_out3); +} + +void hw_init_gpio(void) { + // GPIO clock enable + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); + + // LEDs + palSetPadMode(LED_GREEN_GPIO, LED_GREEN_PIN, + PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); + palSetPadMode(LED_RED_GPIO, LED_RED_PIN, + PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); + + // GPIOA Configuration: Channel 1 to 3 as alternate function push-pull + palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | + PAL_STM32_OSPEED_HIGHEST | + PAL_STM32_PUDR_FLOATING); + + // Hall sensors + palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP); + palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP); + palSetPadMode(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, PAL_MODE_INPUT_PULLUP); + + // Phase filters +// palSetPadMode(PHASE_FILTER_GPIO, PHASE_FILTER_PIN,PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); +// PHASE_FILTER_OFF(); + + // Phase filters + palSetPadMode(GPIOC, 13, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); + palSetPadMode(GPIOC, 14, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); + palSetPadMode(GPIOC, 15, PAL_MODE_OUTPUT_OPENDRAIN | PAL_STM32_OSPEED_HIGHEST); + PHASE_FILTER_OFF(); + + // ADC Pins + palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_ANALOG); + + palSetPadMode(GPIOB, 0, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOB, 1, PAL_MODE_INPUT_ANALOG); + + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 4, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 5, PAL_MODE_INPUT_ANALOG); + + // DAC as voltage reference for shunt amps + palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); + DAC->CR |= DAC_CR_EN1; + DAC->DHR12R1 = 2047; + + palSetPadMode(OUT_1_GPIO, OUT_1_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); + palSetPadMode(OUT_2_GPIO, OUT_2_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); + palSetPadMode(OUT_3_GPIO, OUT_3_PIN, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); + + OUT_1_OFF(); + OUT_2_OFF(); + OUT_3_OFF(); + + lispif_add_ext_load_callback(load_extensions); +} + +void hw_setup_adc_channels(void) { + // ADC1 regular channels + ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles); //0 + ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 2, ADC_SampleTime_15Cycles); //3 + ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 3, ADC_SampleTime_15Cycles); //6 + ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 4, ADC_SampleTime_15Cycles); //9 + ADC_RegularChannelConfig(ADC1, ADC_Channel_Vrefint, 5, ADC_SampleTime_15Cycles); //12 + ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 6, ADC_SampleTime_15Cycles); //15 + + // ADC2 regular channels + ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles); //1 + ADC_RegularChannelConfig(ADC2, ADC_Channel_1, 2, ADC_SampleTime_15Cycles); //4 + ADC_RegularChannelConfig(ADC2, ADC_Channel_6, 3, ADC_SampleTime_15Cycles); //7 + ADC_RegularChannelConfig(ADC2, ADC_Channel_15, 4, ADC_SampleTime_15Cycles); //10 + ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 5, ADC_SampleTime_15Cycles); //13 + ADC_RegularChannelConfig(ADC2, ADC_Channel_9, 6, ADC_SampleTime_15Cycles); //16 + + // ADC3 regular channels + ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles); //2 + ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 2, ADC_SampleTime_15Cycles); //5 + ADC_RegularChannelConfig(ADC3, ADC_Channel_3, 3, ADC_SampleTime_15Cycles); //8 + ADC_RegularChannelConfig(ADC3, ADC_Channel_13, 4, ADC_SampleTime_15Cycles); //11 + ADC_RegularChannelConfig(ADC3, ADC_Channel_1, 5, ADC_SampleTime_15Cycles); //14 + ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 6, ADC_SampleTime_15Cycles); //17 + + // Injected channels + ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 3, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 3, ADC_SampleTime_15Cycles); + ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles); +} + +void hw_start_i2c(void) { + i2cAcquireBus(&HW_I2C_DEV); + + if (!i2c_running) { + palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, + PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) | + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, + PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) | + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + + i2cStart(&HW_I2C_DEV, &i2cfg); + i2c_running = true; + } + + i2cReleaseBus(&HW_I2C_DEV); +} + +void hw_stop_i2c(void) { + i2cAcquireBus(&HW_I2C_DEV); + + if (i2c_running) { + palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, PAL_MODE_INPUT); + palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, PAL_MODE_INPUT); + + i2cStop(&HW_I2C_DEV); + i2c_running = false; + + } + + i2cReleaseBus(&HW_I2C_DEV); +} + +/** + * Try to restore the i2c bus + */ +void hw_try_restore_i2c(void) { + if (i2c_running) { + i2cAcquireBus(&HW_I2C_DEV); + + palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + + palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + + palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN); + palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN); + + chThdSleep(1); + + for(int i = 0;i < 16;i++) { + palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN); + chThdSleep(1); + palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN); + chThdSleep(1); + } + + // Generate start then stop condition + palClearPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN); + chThdSleep(1); + palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN); + chThdSleep(1); + palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN); + chThdSleep(1); + palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN); + + palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, + PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) | + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + + palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, + PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) | + PAL_STM32_OTYPE_OPENDRAIN | + PAL_STM32_OSPEED_MID1 | + PAL_STM32_PUDR_PULLUP); + + HW_I2C_DEV.state = I2C_STOP; + i2cStart(&HW_I2C_DEV, &i2cfg); + + i2cReleaseBus(&HW_I2C_DEV); + } +} + diff --git a/hwconf/vesc/basic/hw_basic_core.h b/hwconf/vesc/basic/hw_basic_core.h new file mode 100644 index 00000000..9528ba09 --- /dev/null +++ b/hwconf/vesc/basic/hw_basic_core.h @@ -0,0 +1,265 @@ +/* + Copyright 2023 Benjamin Vedder benjamin@vedder.se + + This file is part of the VESC firmware. + + The VESC firmware is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + The VESC firmware is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + */ + +#ifndef HW_BASIC_CORE_H_ +#define HW_BASIC_CORE_H_ + +#ifdef HW_BASIC + #define HW_NAME "VESC_BASIC" +#else + #error "Must define hardware type" +#endif + +// HW properties +#define HW_HAS_3_SHUNTS +#define HW_HAS_PHASE_FILTERS +#define INVERTED_SHUNT_POLARITY + +// Macros +#define LED_GREEN_GPIO GPIOB +#define LED_GREEN_PIN 7 +#define LED_RED_GPIO GPIOB +#define LED_RED_PIN 5 + +#define LED_GREEN_ON() palSetPad(LED_GREEN_GPIO, LED_GREEN_PIN) +#define LED_GREEN_OFF() palClearPad(LED_GREEN_GPIO, LED_GREEN_PIN) +#define LED_RED_ON() palSetPad(LED_RED_GPIO, LED_RED_PIN) +#define LED_RED_OFF() palClearPad(LED_RED_GPIO, LED_RED_PIN) + +#define PHASE_FILTER_GPIO GPIOC +#define PHASE_FILTER_PIN 15 + +// Phase filter +#define PHASE_FILTER_OFF() palSetPad(GPIOC, 13); palSetPad(GPIOC, 14); palSetPad(GPIOC, 15) +#define PHASE_FILTER_ON() palClearPad(GPIOC, 13); palClearPad(GPIOC, 14); palClearPad(GPIOC, 15) + +// Output1 +#define OUT_1_GPIO GPIOC +#define OUT_1_PIN 10 +#define OUT_1_ON() palSetPad(OUT_1_GPIO, OUT_1_PIN) +#define OUT_1_OFF() palClearPad(OUT_1_GPIO, OUT_1_PIN) + +// Output2 +#define OUT_2_GPIO GPIOC +#define OUT_2_PIN 11 +#define OUT_2_ON() palSetPad(OUT_2_GPIO, OUT_2_PIN) +#define OUT_2_OFF() palClearPad(OUT_2_GPIO, OUT_2_PIN) + +// Output3 +#define OUT_3_GPIO GPIOA +#define OUT_3_PIN 15 +#define OUT_3_ON() palSetPad(OUT_3_GPIO, OUT_3_PIN) +#define OUT_3_OFF() palClearPad(OUT_3_GPIO, OUT_3_PIN) + +/* + * ADC Vector + * + * 0 (1): IN10 CURR1 + * 1 (2): IN11 CURR2 + * 2 (3): IN12 CURR3 + * 3 (1): IN0 SENS1 + * 4 (2): IN1 SENS2 + * 5 (3): IN2 SENS3 + * 6 (1): IN5 + * 7 (2): IN6 + * 8 (3): IN3 + * 9 (1): IN14 + * 10 (2): IN15 + * 11 (3): IN13 + * 12 (1): Vrefint + * 13 (2): IN0 + * 14 (3): IN1 + * 15 (1): IN8 + * 16 (2): IN9 + * 17 (3): IN2 + */ + +#define HW_ADC_CHANNELS 18 +#define HW_ADC_INJ_CHANNELS 3 +#define HW_ADC_NBR_CONV 6 + +// ADC Indexes +#define ADC_IND_SENS1 3 +#define ADC_IND_SENS2 4 +#define ADC_IND_SENS3 5 +#define ADC_IND_CURR1 0 +#define ADC_IND_CURR2 1 +#define ADC_IND_CURR3 2 +#define ADC_IND_VIN_SENS 11 +#define ADC_IND_EXT 8 +#define ADC_IND_EXT2 15 +#define ADC_IND_TEMP_MOS 10 +#define ADC_IND_TEMP_MOTOR 16 +#define ADC_IND_VREFINT 12 + +// ADC macros and settings + +// Component parameters (can be overridden) +#ifndef V_REG +#define V_REG 3.3 +#endif +#ifndef VIN_R1 +#define VIN_R1 150000.0 +#endif +#ifndef VIN_R2 +#define VIN_R2 4700.0 +#endif +#ifndef CURRENT_AMP_GAIN +#define CURRENT_AMP_GAIN 20.0 +#endif +#ifndef CURRENT_SHUNT_RES +#define CURRENT_SHUNT_RES 0.0005 +#endif + +// Input voltage +#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2)) + +// NTC Termistors +#define NTC_RES(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // MOS temp sensor on low side //((4095.0 * 10000.0) / adc_val - 10000.0) +#define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15) + +#define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side +#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15) + +// Voltage on ADC channel +#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4095.0 * V_REG) + +// COMM-port ADC GPIOs +#define HW_ADC_EXT_GPIO GPIOA +#define HW_ADC_EXT_PIN 3 +#define HW_ADC_EXT2_GPIO GPIOA +#define HW_ADC_EXT2_PIN 6 + +// UART Peripheral +#define HW_UART_DEV SD3 +#define HW_UART_GPIO_AF GPIO_AF_USART3 +#define HW_UART_TX_PORT GPIOB +#define HW_UART_TX_PIN 10 +#define HW_UART_RX_PORT GPIOB +#define HW_UART_RX_PIN 11 + +// ICU Peripheral for servo decoding +#define HW_USE_SERVO_TIM4 +#define HW_ICU_TIMER TIM4 +#define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE) +#define HW_ICU_DEV ICUD4 +#define HW_ICU_CHANNEL ICU_CHANNEL_1 +#define HW_ICU_GPIO_AF GPIO_AF_TIM4 +#define HW_ICU_GPIO GPIOB +#define HW_ICU_PIN 6 + +// IMU +#define LSM6DS3_NSS_GPIO GPIOC +#define LSM6DS3_NSS_PIN 4 +#define LSM6DS3_SCK_GPIO GPIOA +#define LSM6DS3_SCK_PIN 6 +#define LSM6DS3_MOSI_GPIO GPIOA +#define LSM6DS3_MOSI_PIN 5 +#define LSM6DS3_MISO_GPIO GPIOB +#define LSM6DS3_MISO_PIN 2 + +// I2C Peripheral +#define HW_I2C_DEV I2CD2 +#define HW_I2C_GPIO_AF GPIO_AF_I2C2 +#define HW_I2C_SCL_PORT GPIOB +#define HW_I2C_SCL_PIN 10 +#define HW_I2C_SDA_PORT GPIOB +#define HW_I2C_SDA_PIN 11 + +// Hall/encoder pins +#define HW_HALL_ENC_GPIO1 GPIOC +#define HW_HALL_ENC_PIN1 6 +#define HW_HALL_ENC_GPIO2 GPIOC +#define HW_HALL_ENC_PIN2 7 +#define HW_HALL_ENC_GPIO3 GPIOC +#define HW_HALL_ENC_PIN3 8 +#define HW_ENC_TIM TIM3 +#define HW_ENC_TIM_AF GPIO_AF_TIM3 +#define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE) +#define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC +#define HW_ENC_EXTI_PINSRC EXTI_PinSource8 +#define HW_ENC_EXTI_CH EXTI9_5_IRQn +#define HW_ENC_EXTI_LINE EXTI_Line8 +#define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler +#define HW_ENC_TIM_ISR_CH TIM3_IRQn +#define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler + +// SPI pins //Replicated from the IMU +#define HW_SPI_DEV SPID1 +#define HW_SPI_GPIO_AF GPIO_AF_SPI1 +#define HW_SPI_PORT_NSS GPIOB +#define HW_SPI_PIN_NSS 11 +#define HW_SPI_PORT_SCK GPIOA +#define HW_SPI_PIN_SCK 5 +#define HW_SPI_PORT_MOSI GPIOB +#define HW_SPI_PIN_MOSI 2 +#define HW_SPI_PORT_MISO GPIOA +#define HW_SPI_PIN_MISO 6 + +// Measurement macros +#define ADC_V_L1 ADC_Value[ADC_IND_SENS1] +#define ADC_V_L2 ADC_Value[ADC_IND_SENS2] +#define ADC_V_L3 ADC_Value[ADC_IND_SENS3] +#define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2) + +// Macros +#define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1) +#define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2) +#define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3) + +// Override dead time. See the stm32f4 reference manual for calculating this value. +#define HW_DEAD_TIME_NSEC 200.0 + +// Default setting overrides +#ifndef MCCONF_L_MIN_VOLTAGE +#define MCCONF_L_MIN_VOLTAGE 15.0 // Minimum voltage input +#endif +#ifndef MCCONF_L_MAX_VOLTAGE +#define MCCONF_L_MAX_VOLTAGE 50.0 // Maximum input voltage +#endif +#ifndef MCCONF_DEFAULT_MOTOR_TYPE +#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC +#endif +#ifndef MCCONF_FOC_F_ZV +#define MCCONF_FOC_F_ZV 30000.0 +#endif +#ifndef MCCONF_L_MAX_ABS_CURRENT +#define MCCONF_L_MAX_ABS_CURRENT 150.0 // The maximum absolute current above which a fault is generated +#endif +#ifndef MCCONF_FOC_SAMPLE_V0_V7 +#define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts) +#endif +#ifndef MCCONF_L_IN_CURRENT_MAX +#define MCCONF_L_IN_CURRENT_MAX 30.0 // Input current limit in Amperes (Upper) +#endif +#ifndef MCCONF_L_IN_CURRENT_MIN +#define MCCONF_L_IN_CURRENT_MIN -30.0 // Input current limit in Amperes (Lower) +#endif + +// Setting limits +#define HW_LIM_CURRENT -150.0, 150.0 +#define HW_LIM_CURRENT_IN -130.0, 130.0 +#define HW_LIM_CURRENT_ABS 0.0, 160.0 +#define HW_LIM_VIN 11.0, 94.0 +#define HW_LIM_ERPM -200e3, 200e3 +#define HW_LIM_DUTY_MIN 0.0, 0.1 +#define HW_LIM_DUTY_MAX 0.0, 0.99 +#define HW_LIM_TEMP_FET -40.0, 110.0 + +#endif /* HW_BASIC_CORE_H_ */ diff --git a/package_firmware.py b/package_firmware.py index 44445da1..2c84edcb 100755 --- a/package_firmware.py +++ b/package_firmware.py @@ -175,6 +175,8 @@ package_dict["RB"] = [['rb', default_name]] package_dict["STR365"] = [['str365', default_name], ['str365_no_limits', no_limits_name]] package_dict["SPARKF"] = [['sparkf', default_name]] +package_dict["VESC_BASIC"] = [['basic', default_name], + ['basic_no_limits', no_limits_name]] # This is the firmware stub string res_firmwares_string = ' TARGET_DESTINATION_DIRECTORY/TARGET_DESTINATION_FILENAME\n'