From 422e348c1a2996833b31ffb972fb43b62816218a Mon Sep 17 00:00:00 2001
From: "Jeffrey M. Friesen" <jfriesen222@gmail.com>
Date: Sat, 29 May 2021 12:41:59 +0200
Subject: [PATCH] Added things for 100D_V2 hardware variant

---
 build_all/rebuild_all      | 19 +++++++++++++
 conf_general.h             |  1 +
 hwconf/hw_stormcore_100d.c | 11 ++++++++
 hwconf/hw_stormcore_100d.h | 55 +++++++++++++++++++++++++++++++++-----
 4 files changed, 80 insertions(+), 6 deletions(-)

diff --git a/build_all/rebuild_all b/build_all/rebuild_all
index b2b1bb9e..ca81018a 100755
--- a/build_all/rebuild_all
+++ b/build_all/rebuild_all
@@ -409,6 +409,25 @@ make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DH
 cd $DIR
 cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
 
+#################### STORMCORE_100D_V2 ########################
+
+COPYDIR=STORMCORE_100D_V2
+rm -f $COPYDIR/*
+
+# default
+cd $FWPATH
+touch conf_general.h
+make -j8 build_args='-DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
+cd $DIR
+cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default.bin
+
+# default with HW limits disabled
+cd $FWPATH
+touch conf_general.h
+make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
+cd $DIR
+cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
+
 #################### STORMCORE_100S ########################
 
 COPYDIR=STORMCORE_100S
diff --git a/conf_general.h b/conf_general.h
index 4f337e85..01287aa1 100644
--- a/conf_general.h
+++ b/conf_general.h
@@ -145,6 +145,7 @@
 //#define HW_HEADER "hw_uxv_sr.h"
 
 //#define HW_DUAL_CONFIG_PARALLEL
+//#define HW_VER_IS_100D_V2
 //#define HW_SOURCE "hw_stormcore_100d.c"
 //#define HW_HEADER "hw_stormcore_100d.h"
 
diff --git a/hwconf/hw_stormcore_100d.c b/hwconf/hw_stormcore_100d.c
index 192c87bf..1ceda36c 100644
--- a/hwconf/hw_stormcore_100d.c
+++ b/hwconf/hw_stormcore_100d.c
@@ -60,6 +60,17 @@ void hw_init_gpio(void) {
 	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
 	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
 
+#ifdef HW_VER_IS_100D_V2
+    palSetPadMode(PHASE_FILTER_GPIO, PHASE_FILTER_PIN,
+                  PAL_MODE_OUTPUT_PUSHPULL |
+                  PAL_STM32_OSPEED_HIGHEST);
+    PHASE_FILTER_OFF();
+    palSetPadMode(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2,
+            PAL_MODE_OUTPUT_PUSHPULL |
+            PAL_STM32_OSPEED_HIGHEST);
+    PHASE_FILTER_OFF_M2();
+#endif
+
 
 
 
diff --git a/hwconf/hw_stormcore_100d.h b/hwconf/hw_stormcore_100d.h
index 331a4543..5843b497 100644
--- a/hwconf/hw_stormcore_100d.h
+++ b/hwconf/hw_stormcore_100d.h
@@ -25,6 +25,8 @@
 
 #ifdef HW_HAS_DUAL_PARALLEL
 #define HW_NAME                 "STORMCORE_100D_PARALLEL"
+#elif defined(HW_VER_IS_100D_V2)
+#define HW_NAME                 "STORMCORE_100D_V2"
 #else
 #define HW_NAME                 "STORMCORE_100D"
 #endif
@@ -69,6 +71,18 @@
 
 #define SMART_SWITCH_MSECS_PRESSED_OFF		2000
 
+#ifdef HW_VER_IS_100D_V2
+#define HW_HAS_PHASE_FILTERS
+#define PHASE_FILTER_GPIO               GPIOE
+#define PHASE_FILTER_PIN                1
+#define PHASE_FILTER_GPIO_M2            GPIOE
+#define PHASE_FILTER_PIN_M2             4
+#define PHASE_FILTER_ON()               palSetPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
+#define PHASE_FILTER_OFF()              palClearPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
+#define PHASE_FILTER_ON_M2()            palSetPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
+#define PHASE_FILTER_OFF_M2()           palClearPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
+#endif
+
 
 
 #define HW_SHUTDOWN_HOLD_ON();
@@ -96,6 +110,17 @@
 #define HW_UART_P_RX_PORT			GPIOA
 #define HW_UART_P_RX_PIN			10
 
+#ifdef HW_VER_IS_100D_V2
+//Pins for Third UART
+#define HW_UART_3_BAUD              115200
+#define HW_UART_3_DEV               SD2
+#define HW_UART_3_GPIO_AF           GPIO_AF_USART2
+#define HW_UART_3_TX_PORT           GPIOD
+#define HW_UART_3_TX_PIN            6
+#define HW_UART_3_RX_PORT           GPIOD
+#define HW_UART_3_RX_PIN            5
+#endif
+
 // SPI for DRV8301
 #define DRV8323S_MOSI_GPIO			GPIOC
 #define DRV8323S_MOSI_PIN			12
@@ -226,11 +251,22 @@
 #ifndef VIN_R2
 #define VIN_R2					2200.0
 #endif
+
+
+#ifdef HW_VER_IS_100D_V2
 #ifndef CURRENT_AMP_GAIN
-#define CURRENT_AMP_GAIN		10.0
+#define CURRENT_AMP_GAIN        20.0
 #endif
 #ifndef CURRENT_SHUNT_RES
-#define CURRENT_SHUNT_RES		0.001
+#define CURRENT_SHUNT_RES       0.0005
+#endif
+#else
+#ifndef CURRENT_AMP_GAIN
+#define CURRENT_AMP_GAIN        10.0
+#endif
+#ifndef CURRENT_SHUNT_RES
+#define CURRENT_SHUNT_RES       0.001
+#endif
 #endif
 
 #define VBATT_R1					360000.0
@@ -334,10 +370,17 @@
 #define NRF_PIN_MISO            10
 
 // NRF SWD
-#define NRF5x_SWDIO_GPIO		GPIOD
-#define NRF5x_SWDIO_PIN			6
-#define NRF5x_SWCLK_GPIO		GPIOD
-#define NRF5x_SWCLK_PIN			5
+#ifdef HW_VER_IS_100D_V2
+#define NRF5x_SWDIO_GPIO        GPIOD
+#define NRF5x_SWDIO_PIN         9
+#define NRF5x_SWCLK_GPIO        GPIOD
+#define NRF5x_SWCLK_PIN         8
+#else
+#define NRF5x_SWDIO_GPIO        GPIOD
+#define NRF5x_SWDIO_PIN         6
+#define NRF5x_SWCLK_GPIO        GPIOD
+#define NRF5x_SWCLK_PIN         5
+#endif
 
 #ifndef MCCONF_DEFAULT_MOTOR_TYPE
 #define MCCONF_DEFAULT_MOTOR_TYPE	MOTOR_TYPE_FOC