Some fixes after the merge

This commit is contained in:
Benjamin Vedder 2019-02-19 18:55:18 +01:00
parent a546cc4dd5
commit c76942009b
33 changed files with 124 additions and 110 deletions

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@ -11,7 +11,7 @@
An open source motor controller firmware.
This is the source code for the VESC DC/BLDC/FOC controller. Read more at
[http://vesc-project.com/](http://vesc-project.com/)
[https://vesc-project.com/](https://vesc-project.com/)
## Supported boards

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@ -7,7 +7,7 @@ DIR=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )
################## HW 46 & 47 #######################
COPYDIR=46_o_47
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -54,7 +54,7 @@ cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_servoout.bin
#################### HW 48 ########################
COPYDIR=48
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -87,7 +87,7 @@ cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_servoout.bin
#################### HW 410 & 411 & 412 ########################
COPYDIR=410_o_411_o_412
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -127,7 +127,7 @@ cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_servoout.bin
#################### HW 60 ########################
COPYDIR=60
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -165,7 +165,7 @@ cd $DIR
#################### HW DAS_RS ########################
COPYDIR=DAS_RS
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -182,7 +182,7 @@ cd $DIR
#################### HW 75_300 ########################
COPYDIR=75_300
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH
@ -220,7 +220,7 @@ cd $DIR
#################### HW PALTA ########################
COPYDIR=PALTA
rm $COPYDIR/*
rm -f $COPYDIR/*
# default
cd $FWPATH

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@ -51,7 +51,7 @@ static THD_WORKING_AREA(detect_thread_wa, 2048);
static thread_t *detect_tp;
// Private variables
static uint8_t send_buffer[PACKET_MAX_PL_LEN];
static uint8_t send_buffer_global[PACKET_MAX_PL_LEN];
static uint8_t detect_thread_cmd_buffer[50];
static volatile bool is_detecting = false;
static void(* volatile send_func)(unsigned char *data, unsigned int len) = 0;
@ -129,6 +129,7 @@ void commands_process_packet(unsigned char *data, unsigned int len) {
int32_t ind = 0;
static mc_configuration mcconf; // Static to save some stack space
static app_configuration appconf;
uint8_t *send_buffer = send_buffer_global;
packet_id = data[0];
data++;
@ -472,6 +473,7 @@ void commands_process_packet(unsigned char *data, unsigned int len) {
mcconf.m_dc_f_sw = buffer_get_float32_auto(data, &ind);
mcconf.m_ntc_motor_beta = buffer_get_float32_auto(data, &ind);
mcconf.m_out_aux_mode = data[ind++];
mcconf.si_motor_poles = data[ind++];
mcconf.si_gear_ratio = buffer_get_float32_auto(data, &ind);
mcconf.si_wheel_diameter = buffer_get_float32_auto(data, &ind);
@ -1083,21 +1085,23 @@ void commands_set_app_data_handler(void(*func)(unsigned char *data, unsigned int
void commands_send_app_data(unsigned char *data, unsigned int len) {
int32_t index = 0;
send_buffer[index++] = COMM_CUSTOM_APP_DATA;
memcpy(send_buffer + index, data, len);
send_buffer_global[index++] = COMM_CUSTOM_APP_DATA;
memcpy(send_buffer_global + index, data, len);
index += len;
commands_send_packet(send_buffer, index);
commands_send_packet(send_buffer_global, index);
}
void commands_send_gpd_buffer_notify(void) {
int32_t index = 0;
send_buffer[index++] = COMM_GPD_BUFFER_NOTIFY;
commands_send_packet(send_buffer, index);
send_buffer_global[index++] = COMM_GPD_BUFFER_NOTIFY;
commands_send_packet(send_buffer_global, index);
}
void commands_send_mcconf(COMM_PACKET_ID packet_id, mc_configuration *mcconf) {
int32_t ind = 0;
uint8_t *send_buffer = send_buffer_global;
send_buffer[ind++] = packet_id;
send_buffer[ind++] = mcconf->pwm_mode;
@ -1226,6 +1230,8 @@ void commands_send_mcconf(COMM_PACKET_ID packet_id, mc_configuration *mcconf) {
void commands_send_appconf(COMM_PACKET_ID packet_id, app_configuration *appconf) {
int32_t ind = 0;
uint8_t *send_buffer = send_buffer_global;
send_buffer[ind++] = packet_id;
send_buffer[ind++] = appconf->controller_id;
buffer_append_uint32(send_buffer, appconf->timeout_msec, &ind);
@ -1388,7 +1394,7 @@ static THD_FUNCTION(detect_thread, arg) {
detect_coupling_k = 0.0;
}
int32_t ind = 0;
ind = 0;
send_buffer[ind++] = COMM_DETECT_MOTOR_PARAM;
buffer_append_int32(send_buffer, (int32_t)(detect_cycle_int_limit * 1000.0), &ind);
buffer_append_int32(send_buffer, (int32_t)(detect_coupling_k * 1000.0), &ind);

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@ -806,34 +806,32 @@ bool conf_general_measure_flux_linkage(float current, float duty,
/* Calculate DTG register */
uint8_t conf_general_calculate_deadtime(float deadtime_ns, float core_clock_freq) {
uint8_t DTG = 0;
float timebase = 1/(core_clock_freq/1000000.0)*1000.0;
float timebase = 1.0 / (core_clock_freq / 1000000.0) * 1000.0;
if (deadtime_ns <= (timebase * 127.0) )
DTG = deadtime_ns / timebase;
else {
if (deadtime_ns <= ((63.0 + 64.0)*2.0*timebase) ) {
DTG = deadtime_ns / (2.0*timebase) - 64.0;
DTG |= 0x80;
}
else {
if (deadtime_ns <= ((31.0 + 32.0)*8.0*timebase) ) {
DTG = deadtime_ns / (8.0*timebase) - 32.0;
DTG |= 0xC0;
}
else {
if (deadtime_ns <= ((31.0 + 32)*16*timebase) ) {
DTG = deadtime_ns / (16.0*timebase) - 32.0;
DTG |= 0xE0;
}
else {
// Deadtime requested is longer than max achievable. Set deadtime at
// longest possible value
DTG = 0xFF;
assert_param(1); //catch this
}
}
}
if (deadtime_ns <= (timebase * 127.0)) {
DTG = deadtime_ns / timebase;
} else {
if (deadtime_ns <= ((63.0 + 64.0) * 2.0 * timebase)) {
DTG = deadtime_ns / (2.0 * timebase) - 64.0;
DTG |= 0x80;
} else {
if (deadtime_ns <= ((31.0 + 32.0) * 8.0 * timebase)) {
DTG = deadtime_ns / (8.0 * timebase) - 32.0;
DTG |= 0xC0;
} else {
if (deadtime_ns <= ((31.0 + 32) * 16 * timebase)) {
DTG = deadtime_ns / (16.0 * timebase) - 32.0;
DTG |= 0xE0;
} else {
// Deadtime requested is longer than max achievable. Set deadtime at
// longest possible value
DTG = 0xFF;
assert_param(1); //catch this
}
}
}
}
return DTG;
}
@ -956,21 +954,21 @@ bool conf_general_measure_flux_linkage_openloop(float current, float duty,
float vd_avg = 0.0;
float iq_avg = 0.0;
float id_avg = 0.0;
float samples = 0.0;
float samples2 = 0.0;
for (int i = 0;i < 1000;i++) {
vq_avg += mcpwm_foc_get_vq();
vd_avg += mcpwm_foc_get_vd();
iq_avg += mcpwm_foc_get_iq();
id_avg += mcpwm_foc_get_id();
samples += 1.0;
samples2 += 1.0;
chThdSleepMilliseconds(1);
}
vq_avg /= samples;
vd_avg /= samples;
iq_avg /= samples;
id_avg /= samples;
vq_avg /= samples2;
vd_avg /= samples2;
iq_avg /= samples2;
id_avg /= samples2;
*linkage = (sqrtf(SQ(vq_avg) + SQ(vd_avg)) - res *
sqrtf(SQ(iq_avg) + SQ(id_avg))) / (rpm_now * ((2.0 * M_PI) / 60.0));

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@ -70,8 +70,8 @@
//#define HW_SOURCE "hw_410.c" // Also for 4.11 and 4.12
//#define HW_HEADER "hw_410.h" // Also for 4.11 and 4.12
//#define HW_SOURCE "hw_60.c"
//#define HW_HEADER "hw_60.h"
#define HW_SOURCE "hw_60.c"
#define HW_HEADER "hw_60.h"
//#define HW_SOURCE "hw_r2.c"
//#define HW_HEADER "hw_r2.h"
@ -82,8 +82,8 @@
//#define HW_SOURCE "hw_das_rs.c"
//#define HW_HEADER "hw_das_rs.h"
#define HW_SOURCE "hw_palta.c"
#define HW_HEADER "hw_palta.h"
//#define HW_SOURCE "hw_palta.c"
//#define HW_HEADER "hw_palta.h"
//#define HW_SOURCE "hw_rh.c"
//#define HW_HEADER "hw_rh.h"

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@ -71,4 +71,3 @@ CH_IRQ_HANDLER(PVD_IRQHandler) {
EXTI_ClearFlag(EXTI_Line16);
}
}

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@ -450,8 +450,9 @@ void mcpwm_foc_init(volatile mc_configuration *configuration) {
chThdCreateStatic(timer_thread_wa, sizeof(timer_thread_wa), NORMALPRIO, timer_thread, NULL);
// Check if the system has resumed from IWDG reset
if (timeout_had_IWDG_reset())
if (timeout_had_IWDG_reset()) {
mc_interface_fault_stop(FAULT_CODE_BOOTING_FROM_WATCHDOG_RESET);
}
m_init_done = true;
}
@ -1417,7 +1418,9 @@ bool mcpwm_foc_measure_res_ind(float *res, float *ind) {
}
}
i_last = (m_conf->l_current_max / 2.0);
if (i_last < 0.01) {
i_last = (m_conf->l_current_max / 2.0);
}
*res = mcpwm_foc_measure_resistance(i_last, 200);
*ind = mcpwm_foc_measure_inductance_current(i_last, 200, 0);
@ -1565,10 +1568,11 @@ void mcpwm_foc_adc_int_handler(void *p, uint32_t flags) {
(void)flags;
static int skip = 0;
if (++skip == FOC_CONTROL_LOOP_FREQ_DIVIDER)
if (++skip == FOC_CONTROL_LOOP_FREQ_DIVIDER) {
skip = 0;
else
} else {
return;
}
TIM12->CNT = 0;
@ -1734,9 +1738,14 @@ void mcpwm_foc_adc_int_handler(void *p, uint32_t flags) {
dt = 1.0 / (m_conf->foc_f_sw / 2.0);
}
#else
const float dt = 1.0 / (m_conf->foc_f_sw / 2.0);
float dt = 1.0 / (m_conf->foc_f_sw / 2.0);
#endif
// This has to be done for the skip function to have any chance at working with the
// observer and control loops.
// TODO: Test this.
dt /= (float)FOC_CONTROL_LOOP_FREQ_DIVIDER;
UTILS_LP_FAST(m_motor_state.v_bus, GET_INPUT_VOLTAGE(), 0.1);
float enc_ang = 0;
@ -1957,8 +1966,8 @@ void mcpwm_foc_adc_int_handler(void *p, uint32_t flags) {
float x_tmp = m_motor_state.v_alpha;
float y_tmp = m_motor_state.v_beta;
m_motor_state.v_alpha = x_tmp*COS_MINUS_30_DEG - y_tmp*SIN_MINUS_30_DEG;
m_motor_state.v_beta = x_tmp*SIN_MINUS_30_DEG + y_tmp*COS_MINUS_30_DEG;
m_motor_state.v_alpha = x_tmp * COS_MINUS_30_DEG - y_tmp * SIN_MINUS_30_DEG;
m_motor_state.v_beta = x_tmp * SIN_MINUS_30_DEG + y_tmp * COS_MINUS_30_DEG;
// compensate voltage amplitude
m_motor_state.v_alpha *= ONE_BY_SQRT3;

104
timeout.c
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@ -117,61 +117,61 @@ void timeout_init_IWDT(void) {
}
void timeout_configure_IWDT_slowest(void) {
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0))
{
// Continue to kick the dog
IWDG_ReloadCounter();
}
// Unlock register
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
// Update configuration
IWDG_SetReload(1400);
IWDG_SetPrescaler(IWDG_Prescaler_256);
// Wait for the new configuration to be taken into account
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0))
{
// Continue to kick the dog
IWDG_ReloadCounter();
}
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
// Continue to kick the dog
IWDG_ReloadCounter();
}
// Unlock register
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
// Update configuration
IWDG_SetReload(1400);
IWDG_SetPrescaler(IWDG_Prescaler_256);
// Wait for the new configuration to be taken into account
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
// Continue to kick the dog
IWDG_ReloadCounter();
}
}
void timeout_configure_IWDT(void) {
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0))
{
// Continue to kick the dog
IWDG_ReloadCounter();
}
// Unlock register
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
// Update configuration
IWDG_SetReload(140);
IWDG_SetPrescaler(IWDG_Prescaler_4);
// Wait for the new configuration to be taken into account
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0))
{
// Continue to kick the dog
IWDG_ReloadCounter();
}
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
// Continue to kick the dog
IWDG_ReloadCounter();
}
// Unlock register
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
// Update configuration
IWDG_SetReload(140);
IWDG_SetPrescaler(IWDG_Prescaler_4);
// Wait for the new configuration to be taken into account
while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
// Continue to kick the dog
IWDG_ReloadCounter();
}
}
bool timeout_had_IWDG_reset(void) {
// Check if the system has resumed from IWDG reset
if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST) != RESET) {
/* IWDGRST flag set */
if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST) != RESET) {
/* IWDGRST flag set */
/* Clear reset flags */
RCC_ClearFlag();
RCC_ClearFlag();
return true;
}
}
// Check if the system has resumed from WWDG reset
if (RCC_GetFlagStatus(RCC_FLAG_WWDGRST) != RESET) {
/* IWDGRST flag set */
/* Clear reset flags */
RCC_ClearFlag();
return true;
}
// Check if the system has resumed from WWDG reset
if (RCC_GetFlagStatus(RCC_FLAG_WWDGRST) != RESET) {
/* IWDGRST flag set */
/* Clear reset flags */
RCC_ClearFlag();
return true;
}
return false;
return false;
}
static THD_FUNCTION(timeout_thread, arg) {
@ -193,25 +193,27 @@ static THD_FUNCTION(timeout_thread, arg) {
// Monitored threads (foc, can, timer) must report at least one iteration,
// otherwise the watchdog won't be feed and MCU will reset. All threads should
// be monitored
if(feed_counter[THREAD_MCPWM] < MIN_THREAD_ITERATIONS)
if(feed_counter[THREAD_MCPWM] < MIN_THREAD_ITERATIONS) {
threads_ok = false;
}
#if CAN_ENABLE
if(feed_counter[THREAD_CANBUS] < MIN_THREAD_ITERATIONS)
if(feed_counter[THREAD_CANBUS] < MIN_THREAD_ITERATIONS) {
threads_ok = false;
}
#endif
if(feed_counter[THREAD_TIMER] < MIN_THREAD_ITERATIONS)
if(feed_counter[THREAD_TIMER] < MIN_THREAD_ITERATIONS) {
threads_ok = false;
}
for( int i = 0; i < MAX_THREADS_MONITOR; i++)
for( int i = 0; i < MAX_THREADS_MONITOR; i++) {
feed_counter[i] = 0;
}
if (threads_ok == true) {
// Feed WDT's
WWDG_SetCounter(127); // must reload in >6.24ms and <12.48ms
IWDG_ReloadCounter(); // must reload in <12ms
}
else
{
} else {
// not reloading the watchdog will produce a reset.
// This can be checked from the GUI logs as
// "FAULT_CODE_BOOTING_FROM_WATCHDOG_RESET"