mirror of https://github.com/rusefi/bldc.git
Add CFOC2
This commit is contained in:
Mitch Lustig
parent
80fffdea73
commit
fbe78dfe93
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@ -146,6 +146,10 @@
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//
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//
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//#define HW_SOURCE "hw_stormcore_100s.c"
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//#define HW_SOURCE "hw_stormcore_100s.c"
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//#define HW_HEADER "hw_stormcore_100s.h"
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//#define HW_HEADER "hw_stormcore_100s.h"
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//#define HW_SOURCE "hw_Cheap_FOCer_2.c"
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//#define HW_HEADER "hw_Cheap_FOCer_2.h"
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#endif
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#endif
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#ifndef HW_SOURCE
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#ifndef HW_SOURCE
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@ -66,6 +66,8 @@ void drv8301_init(void) {
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drv8301_write_reg(2, 0x0430);
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drv8301_write_reg(2, 0x0430);
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drv8301_write_reg(2, 0x0430);
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drv8301_write_reg(2, 0x0430);
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drv8301_set_current_amp_gain(CURRENT_AMP_GAIN);
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terminal_register_command_callback(
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terminal_register_command_callback(
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"drv8301_read_reg",
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"drv8301_read_reg",
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"Read a register from the DRV8301 and print it.",
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"Read a register from the DRV8301 and print it.",
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@ -126,6 +128,30 @@ void drv8301_set_oc_mode(drv8301_oc_mode mode) {
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drv8301_write_reg(2, reg);
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drv8301_write_reg(2, reg);
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}
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}
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void drv8301_set_current_amp_gain(int gain) {
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int reg = drv8301_read_reg(3);
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reg &= ~(0x03 << 4);
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switch(gain) {
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case 10:
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reg |= (0 & 0x03) << 2;
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break;
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case 20:
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reg |= (1 & 0x03) << 2;
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break;
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case 40:
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reg |= (2 & 0x03) << 2;
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break;
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case 80:
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reg |= (3 & 0x03) << 2;
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break;
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default:
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//gain not supported
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break;
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}
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drv8301_write_reg(3, reg);
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}
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/**
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/**
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* Read the fault codes of the DRV8301.
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* Read the fault codes of the DRV8301.
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*
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*
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@ -158,6 +184,7 @@ void drv8301_reset_faults(void) {
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int reg = drv8301_read_reg(2);
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int reg = drv8301_read_reg(2);
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reg |= 1 << 2;
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reg |= 1 << 2;
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drv8301_write_reg(2, reg);
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drv8301_write_reg(2, reg);
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drv8301_set_current_amp_gain(CURRENT_AMP_GAIN);
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}
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}
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char* drv8301_faults_to_string(int faults) {
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char* drv8301_faults_to_string(int faults) {
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@ -29,6 +29,7 @@ void drv8301_reset_faults(void);
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char* drv8301_faults_to_string(int faults);
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char* drv8301_faults_to_string(int faults);
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unsigned int drv8301_read_reg(int reg);
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unsigned int drv8301_read_reg(int reg);
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void drv8301_write_reg(int reg, int data);
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void drv8301_write_reg(int reg, int data);
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void drv8301_set_current_amp_gain(int gain);
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// Defines
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// Defines
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#define DRV8301_FAULT_FETLC_OC (1 << 0)
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#define DRV8301_FAULT_FETLC_OC (1 << 0)
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@ -0,0 +1,246 @@
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/*
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Copyright 2012-2016 Benjamin Vedder benjamin@vedder.se
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "ch.h"
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#include "hal.h"
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#include "stm32f4xx_conf.h"
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#include "utils.h"
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#include "drv8301.h"
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// Variables
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static volatile bool i2c_running = false;
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// I2C configuration
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static const I2CConfig i2cfg = {
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OPMODE_I2C,
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100000,
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STD_DUTY_CYCLE
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};
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void hw_init_gpio(void) {
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// GPIO clock enable
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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// LEDs
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palSetPadMode(GPIOB, 0,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(GPIOB, 1,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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// ENABLE_GATE
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#ifdef HW60_VEDDER_FIRST_PCB
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palSetPadMode(GPIOB, 6,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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#else
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palSetPadMode(GPIOB, 5,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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#endif
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ENABLE_GATE();
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// Current filter
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palSetPadMode(GPIOD, 2,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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CURRENT_FILTER_OFF();
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// GPIOA Configuration: Channel 1 to 3 as alternate function push-pull
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palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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// Hall sensors
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palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP);
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palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP);
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palSetPadMode(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, PAL_MODE_INPUT_PULLUP);
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// Fault pin
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palSetPadMode(GPIOB, 7, PAL_MODE_INPUT_PULLUP);
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// ADC Pins
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palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 4, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 5, PAL_MODE_INPUT_ANALOG);
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drv8301_init();
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}
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void hw_setup_adc_channels(void) {
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// ADC1 regular channels
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ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_Vrefint, 5, ADC_SampleTime_15Cycles);
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// ADC2 regular channels
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ADC_RegularChannelConfig(ADC2, ADC_Channel_1, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_6, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_15, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 5, ADC_SampleTime_15Cycles);
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// ADC3 regular channels
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ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_3, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_13, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_1, 5, ADC_SampleTime_15Cycles);
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// Injected channels
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 3, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 3, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles);
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}
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void hw_start_i2c(void) {
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i2cAcquireBus(&HW_I2C_DEV);
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if (!i2c_running) {
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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i2cStart(&HW_I2C_DEV, &i2cfg);
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i2c_running = true;
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}
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i2cReleaseBus(&HW_I2C_DEV);
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}
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void hw_stop_i2c(void) {
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i2cAcquireBus(&HW_I2C_DEV);
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if (i2c_running) {
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, PAL_MODE_INPUT);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, PAL_MODE_INPUT);
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i2cStop(&HW_I2C_DEV);
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i2c_running = false;
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}
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i2cReleaseBus(&HW_I2C_DEV);
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}
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/**
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* Try to restore the i2c bus
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*/
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void hw_try_restore_i2c(void) {
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if (i2c_running) {
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i2cAcquireBus(&HW_I2C_DEV);
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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chThdSleep(1);
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for(int i = 0;i < 16;i++) {
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palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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}
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// Generate start then stop condition
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palClearPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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chThdSleep(1);
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palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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HW_I2C_DEV.state = I2C_STOP;
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i2cStart(&HW_I2C_DEV, &i2cfg);
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i2cReleaseBus(&HW_I2C_DEV);
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}
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}
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@ -0,0 +1,306 @@
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/*
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Copyright 2016 Benjamin Vedder benjamin@vedder.se
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||||||
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This file is part of the VESC firmware.
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||||||
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The VESC firmware is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation, either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
The VESC firmware is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HW_Cheap_FOCer_2
|
||||||
|
#define HW_Cheap_FOCer_2
|
||||||
|
|
||||||
|
#define HW_NAME "Cheap FOCer 2"
|
||||||
|
|
||||||
|
// HW properties
|
||||||
|
#define HW_HAS_DRV8301
|
||||||
|
#define HW_HAS_3_SHUNTS
|
||||||
|
|
||||||
|
// Macros
|
||||||
|
#ifdef HW60_VEDDER_FIRST_PCB
|
||||||
|
#define ENABLE_GATE() palSetPad(GPIOB, 6)
|
||||||
|
#define DISABLE_GATE() palClearPad(GPIOB, 6)
|
||||||
|
#else
|
||||||
|
#define ENABLE_GATE() palSetPad(GPIOB, 5)
|
||||||
|
#define DISABLE_GATE() palClearPad(GPIOB, 5)
|
||||||
|
#endif
|
||||||
|
#define DCCAL_ON()
|
||||||
|
#define DCCAL_OFF()
|
||||||
|
#define IS_DRV_FAULT() (!palReadPad(GPIOB, 7))
|
||||||
|
|
||||||
|
#define LED_GREEN_ON() palSetPad(GPIOB, 0)
|
||||||
|
#define LED_GREEN_OFF() palClearPad(GPIOB, 0)
|
||||||
|
#define LED_RED_ON() palSetPad(GPIOB, 1)
|
||||||
|
#define LED_RED_OFF() palClearPad(GPIOB, 1)
|
||||||
|
|
||||||
|
#define CURRENT_FILTER_ON() palSetPad(GPIOD, 2)
|
||||||
|
#define CURRENT_FILTER_OFF() palClearPad(GPIOD, 2)
|
||||||
|
|
||||||
|
// Switch on current filter if a permanent
|
||||||
|
// NRF24 cannot be found, as the later
|
||||||
|
// HW60 has changed one of the permanent NRF
|
||||||
|
// pins to the current filter activation pin.
|
||||||
|
#define HW_PERMANENT_NRF_FAILED_HOOK() \
|
||||||
|
palSetPadMode(GPIOD, 2, \
|
||||||
|
PAL_MODE_OUTPUT_PUSHPULL | \
|
||||||
|
PAL_STM32_OSPEED_HIGHEST); \
|
||||||
|
CURRENT_FILTER_ON()
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ADC Vector
|
||||||
|
*
|
||||||
|
* 0: IN0 SENS1
|
||||||
|
* 1: IN1 SENS2
|
||||||
|
* 2: IN2 SENS3
|
||||||
|
* 3: IN10 CURR1
|
||||||
|
* 4: IN11 CURR2
|
||||||
|
* 5: IN12 CURR3
|
||||||
|
* 6: IN5 ADC_EXT1
|
||||||
|
* 7: IN6 ADC_EXT2
|
||||||
|
* 8: IN3 TEMP_PCB
|
||||||
|
* 9: IN14 TEMP_MOTOR
|
||||||
|
* 10: IN15 ADC_EXT3
|
||||||
|
* 11: IN13 AN_IN
|
||||||
|
* 12: Vrefint
|
||||||
|
* 13: IN0 SENS1
|
||||||
|
* 14: IN1 SENS2
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define HW_ADC_CHANNELS 15
|
||||||
|
#define HW_ADC_INJ_CHANNELS 3
|
||||||
|
#define HW_ADC_NBR_CONV 5
|
||||||
|
|
||||||
|
// ADC Indexes
|
||||||
|
#define ADC_IND_SENS1 0
|
||||||
|
#define ADC_IND_SENS2 1
|
||||||
|
#define ADC_IND_SENS3 2
|
||||||
|
#define ADC_IND_CURR1 3
|
||||||
|
#define ADC_IND_CURR2 4
|
||||||
|
#define ADC_IND_CURR3 5
|
||||||
|
#define ADC_IND_VIN_SENS 11
|
||||||
|
#define ADC_IND_EXT 6
|
||||||
|
#define ADC_IND_EXT2 7
|
||||||
|
#define ADC_IND_TEMP_MOS 8
|
||||||
|
#define ADC_IND_TEMP_MOTOR 9
|
||||||
|
#define ADC_IND_VREFINT 12
|
||||||
|
|
||||||
|
// ADC macros and settings
|
||||||
|
|
||||||
|
// Component parameters (can be overridden)
|
||||||
|
#ifndef V_REG
|
||||||
|
#define V_REG 3.3
|
||||||
|
#endif
|
||||||
|
#ifndef VIN_R1
|
||||||
|
#define VIN_R1 39000.0
|
||||||
|
#endif
|
||||||
|
#ifndef VIN_R2
|
||||||
|
#define VIN_R2 2200.0
|
||||||
|
#endif
|
||||||
|
#ifndef CURRENT_AMP_GAIN
|
||||||
|
#define CURRENT_AMP_GAIN 20
|
||||||
|
#endif
|
||||||
|
#ifndef CURRENT_SHUNT_RES
|
||||||
|
#define CURRENT_SHUNT_RES 0.0005
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Input voltage
|
||||||
|
#define GET_INPUT_VOLTAGE() ((V_REG / 4095.0) * (float)ADC_Value[ADC_IND_VIN_SENS] * ((VIN_R1 + VIN_R2) / VIN_R2))
|
||||||
|
|
||||||
|
// NTC Termistors
|
||||||
|
#define NTC_RES(adc_val) ((4095.0 * 10000.0) / adc_val - 10000.0)
|
||||||
|
#define NTC_TEMP(adc_ind) (1.0 / ((logf(NTC_RES(ADC_Value[adc_ind]) / 10000.0) / 3380.0) + (1.0 / 298.15)) - 273.15)
|
||||||
|
|
||||||
|
#define NTC_RES_MOTOR(adc_val) (10000.0 / ((4095.0 / (float)adc_val) - 1.0)) // Motor temp sensor on low side
|
||||||
|
#define NTC_TEMP_MOTOR(beta) (1.0 / ((logf(NTC_RES_MOTOR(ADC_Value[ADC_IND_TEMP_MOTOR]) / 10000.0) / beta) + (1.0 / 298.15)) - 273.15)
|
||||||
|
|
||||||
|
// Voltage on ADC channel
|
||||||
|
#define ADC_VOLTS(ch) ((float)ADC_Value[ch] / 4096.0 * V_REG)
|
||||||
|
|
||||||
|
// Double samples in beginning and end for positive current measurement.
|
||||||
|
// Useful when the shunt sense traces have noise that causes offset.
|
||||||
|
#ifndef CURR1_DOUBLE_SAMPLE
|
||||||
|
#define CURR1_DOUBLE_SAMPLE 0
|
||||||
|
#endif
|
||||||
|
#ifndef CURR2_DOUBLE_SAMPLE
|
||||||
|
#define CURR2_DOUBLE_SAMPLE 0
|
||||||
|
#endif
|
||||||
|
#ifndef CURR3_DOUBLE_SAMPLE
|
||||||
|
#define CURR3_DOUBLE_SAMPLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Current ADC macros. Override them for custom current measurement functions.
|
||||||
|
#ifndef GET_CURRENT1
|
||||||
|
#ifdef INVERTED_SHUNT_POLARITY
|
||||||
|
#define GET_CURRENT1() (4095 - ADC_Value[ADC_IND_CURR1])
|
||||||
|
#else
|
||||||
|
#define GET_CURRENT1() ADC_Value[ADC_IND_CURR1]
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#ifndef GET_CURRENT2
|
||||||
|
#ifdef INVERTED_SHUNT_POLARITY
|
||||||
|
#define GET_CURRENT2() (4095 - ADC_Value[ADC_IND_CURR2])
|
||||||
|
#else
|
||||||
|
#define GET_CURRENT2() ADC_Value[ADC_IND_CURR2]
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#ifndef GET_CURRENT3
|
||||||
|
#ifdef INVERTED_SHUNT_POLARITY
|
||||||
|
#define GET_CURRENT3() (4095 - ADC_Value[ADC_IND_CURR3])
|
||||||
|
#else
|
||||||
|
#define GET_CURRENT3() ADC_Value[ADC_IND_CURR3]
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// UART Peripheral
|
||||||
|
#define HW_UART_DEV SD3
|
||||||
|
#define HW_UART_GPIO_AF GPIO_AF_USART3
|
||||||
|
#define HW_UART_TX_PORT GPIOB
|
||||||
|
#define HW_UART_TX_PIN 10
|
||||||
|
#define HW_UART_RX_PORT GPIOB
|
||||||
|
#define HW_UART_RX_PIN 11
|
||||||
|
|
||||||
|
// ICU Peripheral for servo decoding
|
||||||
|
#define HW_USE_SERVO_TIM4
|
||||||
|
#define HW_ICU_TIMER TIM4
|
||||||
|
#define HW_ICU_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE)
|
||||||
|
#define HW_ICU_DEV ICUD4
|
||||||
|
#define HW_ICU_CHANNEL ICU_CHANNEL_1
|
||||||
|
#define HW_ICU_GPIO_AF GPIO_AF_TIM4
|
||||||
|
#define HW_ICU_GPIO GPIOB
|
||||||
|
#define HW_ICU_PIN 6
|
||||||
|
|
||||||
|
// I2C Peripheral
|
||||||
|
#define HW_I2C_DEV I2CD2
|
||||||
|
#define HW_I2C_GPIO_AF GPIO_AF_I2C2
|
||||||
|
#define HW_I2C_SCL_PORT GPIOB
|
||||||
|
#define HW_I2C_SCL_PIN 10
|
||||||
|
#define HW_I2C_SDA_PORT GPIOB
|
||||||
|
#define HW_I2C_SDA_PIN 11
|
||||||
|
|
||||||
|
// Hall/encoder pins
|
||||||
|
#define HW_HALL_ENC_GPIO1 GPIOC
|
||||||
|
#define HW_HALL_ENC_PIN1 6
|
||||||
|
#define HW_HALL_ENC_GPIO2 GPIOC
|
||||||
|
#define HW_HALL_ENC_PIN2 7
|
||||||
|
#define HW_HALL_ENC_GPIO3 GPIOC
|
||||||
|
#define HW_HALL_ENC_PIN3 8
|
||||||
|
#define HW_ENC_TIM TIM3
|
||||||
|
#define HW_ENC_TIM_AF GPIO_AF_TIM3
|
||||||
|
#define HW_ENC_TIM_CLK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE)
|
||||||
|
#define HW_ENC_EXTI_PORTSRC EXTI_PortSourceGPIOC
|
||||||
|
#define HW_ENC_EXTI_PINSRC EXTI_PinSource8
|
||||||
|
#define HW_ENC_EXTI_CH EXTI9_5_IRQn
|
||||||
|
#define HW_ENC_EXTI_LINE EXTI_Line8
|
||||||
|
#define HW_ENC_EXTI_ISR_VEC EXTI9_5_IRQHandler
|
||||||
|
#define HW_ENC_TIM_ISR_CH TIM3_IRQn
|
||||||
|
#define HW_ENC_TIM_ISR_VEC TIM3_IRQHandler
|
||||||
|
|
||||||
|
// NRF pins
|
||||||
|
#define NRF_PORT_CSN GPIOB
|
||||||
|
#define NRF_PIN_CSN 12
|
||||||
|
#define NRF_PORT_SCK GPIOB
|
||||||
|
#define NRF_PIN_SCK 4
|
||||||
|
#define NRF_PORT_MOSI GPIOB
|
||||||
|
#define NRF_PIN_MOSI 3
|
||||||
|
#define NRF_PORT_MISO GPIOD
|
||||||
|
#define NRF_PIN_MISO 2
|
||||||
|
|
||||||
|
// SPI pins
|
||||||
|
#define HW_SPI_DEV SPID1
|
||||||
|
#define HW_SPI_GPIO_AF GPIO_AF_SPI1
|
||||||
|
#define HW_SPI_PORT_NSS GPIOA
|
||||||
|
#define HW_SPI_PIN_NSS 4
|
||||||
|
#define HW_SPI_PORT_SCK GPIOA
|
||||||
|
#define HW_SPI_PIN_SCK 5
|
||||||
|
#define HW_SPI_PORT_MOSI GPIOA
|
||||||
|
#define HW_SPI_PIN_MOSI 7
|
||||||
|
#define HW_SPI_PORT_MISO GPIOA
|
||||||
|
#define HW_SPI_PIN_MISO 6
|
||||||
|
|
||||||
|
// SPI for DRV8301
|
||||||
|
#define DRV8301_MOSI_GPIO GPIOC
|
||||||
|
#define DRV8301_MOSI_PIN 12
|
||||||
|
#define DRV8301_MISO_GPIO GPIOC
|
||||||
|
#define DRV8301_MISO_PIN 11
|
||||||
|
#define DRV8301_SCK_GPIO GPIOC
|
||||||
|
#define DRV8301_SCK_PIN 10
|
||||||
|
#define DRV8301_CS_GPIO GPIOC
|
||||||
|
#define DRV8301_CS_PIN 9
|
||||||
|
|
||||||
|
// BMI160
|
||||||
|
#define BMI160_SDA_GPIO GPIOB
|
||||||
|
#define BMI160_SDA_PIN 2
|
||||||
|
#define BMI160_SCL_GPIO GPIOA
|
||||||
|
#define BMI160_SCL_PIN 15
|
||||||
|
|
||||||
|
// Measurement macros
|
||||||
|
#define ADC_V_L1 ADC_Value[ADC_IND_SENS1]
|
||||||
|
#define ADC_V_L2 ADC_Value[ADC_IND_SENS2]
|
||||||
|
#define ADC_V_L3 ADC_Value[ADC_IND_SENS3]
|
||||||
|
#define ADC_V_ZERO (ADC_Value[ADC_IND_VIN_SENS] / 2)
|
||||||
|
|
||||||
|
// Macros
|
||||||
|
#define READ_HALL1() palReadPad(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1)
|
||||||
|
#define READ_HALL2() palReadPad(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2)
|
||||||
|
#define READ_HALL3() palReadPad(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3)
|
||||||
|
|
||||||
|
// Default setting overrides
|
||||||
|
#ifndef MCCONF_DEFAULT_MOTOR_TYPE
|
||||||
|
#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_FOC_F_SW
|
||||||
|
#define MCCONF_FOC_F_SW 20000.0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_L_CURRENT_MAX
|
||||||
|
#define MCCONF_L_CURRENT_MAX 60.0 // Current limit in Amperes (Upper)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_L_CURRENT_MIN
|
||||||
|
#define MCCONF_L_CURRENT_MIN -60.0 // Current limit in Amperes (Lower)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_L_MAX_ABS_CURRENT
|
||||||
|
#define MCCONF_L_MAX_ABS_CURRENT 100.0 // The maximum absolute current above which a fault is generated
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_FOC_SAMPLE_V0_V7
|
||||||
|
#define MCCONF_FOC_SAMPLE_V0_V7 false // Run control loop in both v0 and v7 (requires phase shunts)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MCCONF_M_DRV8301_OC_MODE
|
||||||
|
#define MCCONF_M_DRV8301_OC_MODE DRV8301_OC_DISABLED // DRV8301 over current protection mode
|
||||||
|
#endif
|
||||||
|
#ifndef MCCONF_M_DRV8301_OC_ADJ
|
||||||
|
#define MCCONF_M_DRV8301_OC_ADJ 25 // DRV8301 over current protection threshold
|
||||||
|
#endif
|
||||||
|
#ifndef MCCONF_L_LIM_TEMP_FET_START
|
||||||
|
#define MCCONF_L_LIM_TEMP_FET_START 60.0 // MOSFET temperature where current limiting should begin
|
||||||
|
#endif
|
||||||
|
#ifndef MCCONF_L_LIM_TEMP_FET_END
|
||||||
|
#define MCCONF_L_LIM_TEMP_FET_END 70.0 // MOSFET temperature where everything should be shut off
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// Setting limits
|
||||||
|
#define HW_LIM_CURRENT -120.0, 120.0
|
||||||
|
#define HW_LIM_CURRENT_IN -120.0, 120.0
|
||||||
|
#define HW_LIM_CURRENT_ABS 0.0, 160.0
|
||||||
|
#define HW_LIM_VIN 6.0, 57.0
|
||||||
|
#define HW_LIM_ERPM -200e3, 200e3
|
||||||
|
#define HW_LIM_DUTY_MIN 0.0, 0.1
|
||||||
|
#define HW_LIM_DUTY_MAX 0.0, 0.99
|
||||||
|
#define HW_LIM_TEMP_FET -40.0, 110.0
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* HW_Cheap_FOCer_2 */
|
||||||
Loading…
Reference in New Issue