mirror of https://github.com/rusefi/bldc.git
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements the SW-DP specific functions of the
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* ARM Debug Interface v5 Architecure Specification, ARM doc IHI0031A.
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*/
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#include "general.h"
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#include "exception.h"
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#include "adiv5.h"
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#include "swdptap.h"
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#include "target.h"
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#include "target_internal.h"
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#define SWDP_ACK_OK 0x01
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#define SWDP_ACK_WAIT 0x02
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#define SWDP_ACK_FAULT 0x04
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static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr);
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static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp);
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static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
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uint16_t addr, uint32_t value);
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static void adiv5_swdp_abort(ADIv5_DP_t *dp, uint32_t abort);
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int adiv5_swdp_scan(void)
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{
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uint32_t ack;
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target_list_free();
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ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp));
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if (swdptap_init()) {
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free(dp);
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return -1;
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}
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/* Switch from JTAG to SWD mode */
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swdptap_seq_out(0xFFFFFFFF, 16);
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swdptap_seq_out(0xFFFFFFFF, 32);
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swdptap_seq_out(0xFFFFFFFF, 18);
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swdptap_seq_out(0xE79E, 16); /* 0b0111100111100111 */
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swdptap_seq_out(0xFFFFFFFF, 32);
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swdptap_seq_out(0xFFFFFFFF, 18);
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swdptap_seq_out(0, 16);
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/* Read the SW-DP IDCODE register to syncronise */
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/* This could be done with adiv_swdp_low_access(), but this doesn't
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* allow the ack to be checked here. */
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swdptap_seq_out(0xA5, 8);
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ack = swdptap_seq_in(3);
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if((ack != SWDP_ACK_OK) || swdptap_seq_in_parity(&dp->idcode, 32)) {
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DEBUG("\n");
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free(dp);
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return -1;
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}
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dp->dp_read = adiv5_swdp_read;
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dp->error = adiv5_swdp_error;
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dp->low_access = adiv5_swdp_low_access;
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dp->abort = adiv5_swdp_abort;
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adiv5_swdp_error(dp);
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adiv5_dp_init(dp);
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return target_list?1:0;
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}
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static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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{
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if (addr & ADIV5_APnDP) {
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adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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return adiv5_dp_low_access(dp, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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} else {
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return adiv5_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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}
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}
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static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp)
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{
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uint32_t err, clr = 0;
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err = adiv5_swdp_read(dp, ADIV5_DP_CTRLSTAT) &
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(ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
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ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR);
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if(err & ADIV5_DP_CTRLSTAT_STICKYORUN)
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clr |= ADIV5_DP_ABORT_ORUNERRCLR;
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if(err & ADIV5_DP_CTRLSTAT_STICKYCMP)
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clr |= ADIV5_DP_ABORT_STKCMPCLR;
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if(err & ADIV5_DP_CTRLSTAT_STICKYERR)
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clr |= ADIV5_DP_ABORT_STKERRCLR;
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if(err & ADIV5_DP_CTRLSTAT_WDATAERR)
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clr |= ADIV5_DP_ABORT_WDERRCLR;
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adiv5_dp_write(dp, ADIV5_DP_ABORT, clr);
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dp->fault = 0;
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return err;
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}
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static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
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uint16_t addr, uint32_t value)
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{
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bool APnDP = addr & ADIV5_APnDP;
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addr &= 0xff;
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uint32_t request = 0x81;
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uint32_t response = 0;
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uint32_t ack;
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platform_timeout timeout;
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if(APnDP && dp->fault) return 0;
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if(APnDP) request ^= 0x22;
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if(RnW) request ^= 0x24;
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addr &= 0xC;
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request |= (addr << 1) & 0x18;
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if((addr == 4) || (addr == 8))
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request ^= 0x20;
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platform_timeout_set(&timeout, 2000);
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do {
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swdptap_seq_out(request, 8);
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ack = swdptap_seq_in(3);
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} while (ack == SWDP_ACK_WAIT && !platform_timeout_is_expired(&timeout));
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if (ack == SWDP_ACK_WAIT)
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raise_exception(EXCEPTION_TIMEOUT, "SWDP ACK timeout");
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if(ack == SWDP_ACK_FAULT) {
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dp->fault = 1;
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return 0;
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}
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if(ack != SWDP_ACK_OK)
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raise_exception(EXCEPTION_ERROR, "SWDP invalid ACK");
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if(RnW) {
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if(swdptap_seq_in_parity(&response, 32)) /* Give up on parity error */
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raise_exception(EXCEPTION_ERROR, "SWDP Parity error");
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} else {
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swdptap_seq_out_parity(value, 32);
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/* RM0377 Rev. 8 Chapter 27.5.4 for STM32L0x1 states:
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* Because of the asynchronous clock domains SWCLK and HCLK,
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* two extra SWCLK cycles are needed after a write transaction
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* (after the parity bit) to make the write effective
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* internally. These cycles should be applied while driving
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* the line low (IDLE state)
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* This is particularly important when writing the CTRL/STAT
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* for a power-up request. If the next transaction (requiring
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* a power-up) occurs immediately, it will fail.
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*/
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swdptap_seq_out(0, 2);
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}
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return response;
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}
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static void adiv5_swdp_abort(ADIv5_DP_t *dp, uint32_t abort)
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{
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adiv5_dp_write(dp, ADIV5_DP_ABORT, abort);
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}
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