mirror of https://github.com/rusefi/bldc.git
344 lines
10 KiB
C
344 lines
10 KiB
C
/*
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Copyright 2017 Benjamin Vedder benjamin@vedder.se
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#ifdef HW_VERSION_PALTA
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#include "ch.h"
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#include "hal.h"
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#include "stm32f4xx_conf.h"
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#include "stm32f4xx_dac.h"
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#include "stm32f4xx_rcc.h"
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#include "utils.h"
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#include "terminal.h"
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#include "commands.h"
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// Defines
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#define PALTA_FPGA_CLK_PORT GPIOC
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#define PALTA_FPGA_CLK_PIN 9
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// Variables
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static volatile bool i2c_running = false;
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// I2C configuration
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static const I2CConfig i2cfg = {
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OPMODE_I2C,
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100000,
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STD_DUTY_CYCLE
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};
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// Private functions
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static void terminal_cmd_reset_oc(int argc, const char **argv);
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void hw_palta_init_FPGA_CLK(void);
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void hw_palta_setup_dac(void);
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void hw_init_gpio(void) {
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// GPIO clock enable
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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// LEDs
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palSetPadMode(GPIOB, 2,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(GPIOB, 11,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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// ENABLE_GATE
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palSetPadMode(GPIOC, 14,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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ENABLE_GATE();
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// OC latch
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palSetPadMode(PALTA_OC_CLR_PORT, PALTA_OC_CLR_PIN,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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hw_palta_reset_oc();
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//output a 12MHz clock on MCO2
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hw_palta_init_FPGA_CLK();
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// GPIOA Configuration: Channel 1 to 3 as alternate function push-pull
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palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_FLOATING);
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// Hall sensors
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palSetPadMode(HW_HALL_ENC_GPIO1, HW_HALL_ENC_PIN1, PAL_MODE_INPUT_PULLUP);
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palSetPadMode(HW_HALL_ENC_GPIO2, HW_HALL_ENC_PIN2, PAL_MODE_INPUT_PULLUP);
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palSetPadMode(HW_HALL_ENC_GPIO3, HW_HALL_ENC_PIN3, PAL_MODE_INPUT_PULLUP);
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// Fault pin
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palSetPadMode(GPIOB, 12, PAL_MODE_INPUT_PULLUP);
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// ADC Pins
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palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 1, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 3, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOB, 0, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG);
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#ifdef PALTA_USE_DAC
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hw_palta_setup_dac();
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#else
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palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG); // Bridge temperature A
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palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG); // Bridge temperature B
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#endif
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// Register terminal callbacks
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terminal_register_command_callback(
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"palta_reset_oc",
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"Reset latched overcurrent fault.",
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0,
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terminal_cmd_reset_oc);
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}
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void hw_setup_adc_channels(void) {
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// ADC1 regular channels
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ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC1, ADC_Channel_Vrefint, 5, ADC_SampleTime_15Cycles);
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// ADC2 regular channels
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ADC_RegularChannelConfig(ADC2, ADC_Channel_1, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_15, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC2, ADC_Channel_0, 5, ADC_SampleTime_15Cycles);
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// ADC3 regular channels
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ADC_RegularChannelConfig(ADC3, ADC_Channel_2, 1, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_3, 3, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_13, 4, ADC_SampleTime_15Cycles);
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ADC_RegularChannelConfig(ADC3, ADC_Channel_1, 5, ADC_SampleTime_15Cycles);
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// Injected channels
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 2, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC1, ADC_Channel_10, 3, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC2, ADC_Channel_11, 3, ADC_SampleTime_15Cycles);
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ADC_InjectedChannelConfig(ADC3, ADC_Channel_12, 3, ADC_SampleTime_15Cycles);
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}
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void hw_palta_setup_dac(void) {
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DAC_InitTypeDef DAC_InitStructure;
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/* DMA1 clock and GPIOA clock enable (to be used with DAC) */
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 | RCC_AHB1Periph_GPIOA, ENABLE);
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/* DAC Periph clock enable */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
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/* DAC channel 1 & 2 (DAC_OUT1 = PA.4)(DAC_OUT2 = PA.5) configuration */
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palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
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palSetPadMode(GPIOA, 5, PAL_MODE_INPUT_ANALOG);
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DAC_DeInit();
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/* DAC channel 1 and 2 Configuration */
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DAC_InitStructure.DAC_Trigger = DAC_Trigger_None;
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DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
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DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable; // If enabled minimum output voltage is 200mV (!)
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DAC_Init(DAC_Channel_1, &DAC_InitStructure);
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DAC_Init(DAC_Channel_2, &DAC_InitStructure);
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/* Enable DAC Channel 1 and 2 */
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DAC_Cmd(DAC_Channel_1, ENABLE);
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DAC_Cmd(DAC_Channel_2, ENABLE);
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/* Set DAC channel2 DHR12RD register */
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hw_palta_DAC1_setdata(0x800);
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hw_palta_DAC2_setdata(0x800);
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}
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void hw_palta_DAC1_setdata(uint16_t data) {
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DAC_SetChannel1Data(DAC_Align_12b_R, data);
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}
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void hw_palta_DAC2_setdata(uint16_t data) {
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DAC_SetChannel2Data(DAC_Align_12b_R, data);
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}
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void hw_start_i2c(void) {
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i2cAcquireBus(&HW_I2C_DEV);
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if (!i2c_running) {
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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i2cStart(&HW_I2C_DEV, &i2cfg);
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i2c_running = true;
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}
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i2cReleaseBus(&HW_I2C_DEV);
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}
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void hw_stop_i2c(void) {
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i2cAcquireBus(&HW_I2C_DEV);
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if (i2c_running) {
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN, PAL_MODE_INPUT);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN, PAL_MODE_INPUT);
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i2cStop(&HW_I2C_DEV);
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i2c_running = false;
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}
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i2cReleaseBus(&HW_I2C_DEV);
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}
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/**
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* Try to restore the i2c bus
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*/
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void hw_try_restore_i2c(void) {
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if (i2c_running) {
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i2cAcquireBus(&HW_I2C_DEV);
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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chThdSleep(1);
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for(int i = 0;i < 16;i++) {
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palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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}
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// Generate start then stop condition
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palClearPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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chThdSleep(1);
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palClearPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN);
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chThdSleep(1);
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palSetPad(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN);
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palSetPadMode(HW_I2C_SCL_PORT, HW_I2C_SCL_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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palSetPadMode(HW_I2C_SDA_PORT, HW_I2C_SDA_PIN,
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PAL_MODE_ALTERNATE(HW_I2C_GPIO_AF) |
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PAL_STM32_OTYPE_OPENDRAIN |
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PAL_STM32_OSPEED_MID1 |
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PAL_STM32_PUDR_PULLUP);
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HW_I2C_DEV.state = I2C_STOP;
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i2cStart(&HW_I2C_DEV, &i2cfg);
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i2cReleaseBus(&HW_I2C_DEV);
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}
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}
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void hw_palta_reset_oc(void) {
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palClearPad(PALTA_OC_CLR_PORT, PALTA_OC_CLR_PIN);
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chThdSleep(1);
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palSetPad(PALTA_OC_CLR_PORT, PALTA_OC_CLR_PIN);
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}
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static void terminal_cmd_reset_oc(int argc, const char **argv) {
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(void)argc;
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(void)argv;
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hw_palta_reset_oc();
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commands_printf("Palta OC latch reset done!");
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commands_printf(" ");
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}
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void hw_palta_init_FPGA_CLK(void) {
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/* Configure PLLI2S prescalers */
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/* PLLI2S_VCO : VCO_192M */
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/* SAI_CLK(first level) = PLLI2S_VCO/PLLI2SQ = 192/4 = 48 Mhz */
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RCC->PLLI2SCFGR = (192 << 6) | (4 << 28);
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/* Enable PLLI2S Clock */
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RCC_PLLI2SCmd(ENABLE);
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/* Wait till PLLI2S is ready */
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while(RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) == RESET)
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{
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}
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/* Configure MCO2 pin(PC9) in alternate function */
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palSetPadMode(PALTA_FPGA_CLK_PORT, PALTA_FPGA_CLK_PIN, PAL_MODE_ALTERNATE(GPIO_AF_MCO) |
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PAL_STM32_OTYPE_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST |
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PAL_STM32_PUDR_PULLUP);
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// HSE clock selected to output on MCO2 pin(PA8) 48MHz/4 = 12MHz
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RCC_MCO2Config(RCC_MCO2Source_PLLI2SCLK, RCC_MCO2Div_4);
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}
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#endif
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