mirror of https://github.com/rusefi/bldc.git
186 lines
6.7 KiB
C
186 lines
6.7 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __CORTEXM_H
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#define __CORTEXM_H
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#include "target.h"
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#include "adiv5.h"
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extern long cortexm_wait_timeout;
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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/* Cache identification */
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#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xD78)
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#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xD7C)
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#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xD80)
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#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xD84)
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/* Cache maintenance operations */
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#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xF50)
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#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xF68)
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#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xF70)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
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#define CORTEXM_HFSR_FORCED (1 << 30)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1 << 1)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CORTEXM_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
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#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
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/* Bits 15:11 - Reserved */
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#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
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#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
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#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
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#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
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#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
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#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
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#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
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/* Bits 3:1 - Reserved */
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#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
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/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
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/* Bits 32:15 - Reserved */
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/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
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/* Bits 11:8 - NUM_LIT */ /* v7m only */
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/* Bits 7:4 - NUM_CODE1 */
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/* Bits 3:2 - Unspecified */
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#define CORTEXM_FPB_CTRL_KEY (1 << 1)
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#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
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/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */
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#define CORTEXM_DWT_MASK_BYTE (0 << 0)
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#define CORTEXM_DWT_MASK_HALFWORD (1 << 0)
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#define CORTEXM_DWT_MASK_WORD (3 << 0)
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/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
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#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
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#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
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#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
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#define REG_SP 13
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#define REG_LR 14
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#define REG_PC 15
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#define REG_XPSR 16
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#define REG_MSP 17
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#define REG_PSP 18
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#define REG_SPECIAL 19
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#define ARM_THUMB_BREAKPOINT 0xBE00
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#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
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bool cortexm_probe(ADIv5_AP_t *ap, bool forced);
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ADIv5_AP_t *cortexm_ap(target *t);
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bool cortexm_attach(target *t);
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void cortexm_detach(target *t);
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void cortexm_reset(target *t);
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void cortexm_halt_request(target *t);
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void cortexm_halt_resume(target *t, bool step);
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int cortexm_run_stub(target *t, uint32_t loadaddr,
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uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
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int cortexm_mem_write_sized(
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target *t, target_addr dest, const void *src, size_t len, enum align align);
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#endif
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