mirror of https://github.com/rusefi/bldc.git
194 lines
5.9 KiB
C
194 lines
5.9 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ADIV5_H
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#define __ADIV5_H
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#include "jtag_scan.h"
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#define ADIV5_APnDP 0x100
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#define ADIV5_DP_REG(x) (x)
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#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x))
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/* ADIv5 DP Register addresses */
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#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0)
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#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0)
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#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4)
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#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8)
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#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xC)
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#define ADIV5_DP_BANK0 0
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#define ADIV5_DP_BANK1 1
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#define ADIV5_DP_BANK2 2
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#define ADIV5_DP_BANK3 3
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#define ADIV5_DP_BANK4 4
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#define ADIV5_DP_VERSION_MASK 0xf000
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#define ADIV5_DPv1 0x1000
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#define ADIV5_DPv2 0x2000
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/* AP Abort Register (ABORT) */
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/* Bits 31:5 - Reserved */
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#define ADIV5_DP_ABORT_ORUNERRCLR (1 << 4)
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#define ADIV5_DP_ABORT_WDERRCLR (1 << 3)
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#define ADIV5_DP_ABORT_STKERRCLR (1 << 2)
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#define ADIV5_DP_ABORT_STKCMPCLR (1 << 1)
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/* Bits 5:1 - SW-DP only, reserved in JTAG-DP */
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#define ADIV5_DP_ABORT_DAPABORT (1 << 0)
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/* Control/Status Register (CTRLSTAT) */
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1u << 31)
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1u << 30)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1u << 29)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1u << 28)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1u << 27)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1u << 26)
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/* Bits 25:24 - Reserved */
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/* Bits 23:12 - TRNCNT */
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#define ADIV5_DP_CTRLSTAT_TRNCNT
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/* Bits 11:8 - MASKLANE */
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#define ADIV5_DP_CTRLSTAT_MASKLANE
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/* Bits 7:6 - Reserved in JTAG-DP */
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#define ADIV5_DP_CTRLSTAT_WDATAERR (1u << 7)
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#define ADIV5_DP_CTRLSTAT_READOK (1u << 6)
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#define ADIV5_DP_CTRLSTAT_STICKYERR (1u << 5)
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#define ADIV5_DP_CTRLSTAT_STICKYCMP (1u << 4)
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#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3u << 2)
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#define ADIV5_DP_CTRLSTAT_STICKYORUN (1u << 1)
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#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1u << 0)
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/* ADIv5 MEM-AP Registers */
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#define ADIV5_AP_CSW ADIV5_AP_REG(0x00)
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#define ADIV5_AP_TAR ADIV5_AP_REG(0x04)
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/* 0x08 - Reserved */
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#define ADIV5_AP_DRW ADIV5_AP_REG(0x0C)
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#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10 + (4*(x)))
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/* 0x20:0xF0 - Reserved */
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#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4)
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#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8)
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#define ADIV5_AP_IDR ADIV5_AP_REG(0xFC)
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/* AP Control and Status Word (CSW) */
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#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
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/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
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#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1u << 29)
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#define ADIV5_AP_CSW_HPROT1 (1u << 25)
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#define ADIV5_AP_CSW_SPIDEN (1u << 23)
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/* Bits 22:12 - Reserved */
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/* Bits 11:8 - Mode, must be zero */
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#define ADIV5_AP_CSW_TRINPROG (1u << 7)
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#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
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#define ADIV5_AP_CSW_ADDRINC_NONE (0u << 4)
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#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
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#define ADIV5_AP_CSW_ADDRINC_PACKED (2u << 4)
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#define ADIV5_AP_CSW_ADDRINC_MASK (3u << 4)
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/* Bit 3 - Reserved */
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#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
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#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
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#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
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#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
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/* Constants to make RnW parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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enum align {
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ALIGN_BYTE = 0,
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ALIGN_HALFWORD = 1,
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ALIGN_WORD = 2,
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ALIGN_DWORD = 3
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};
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/* Try to keep this somewhat absract for later adding SW-DP */
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typedef struct ADIv5_DP_s {
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int refcnt;
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uint32_t idcode;
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uint32_t dp_idcode; /* Contains DPvX revision*/
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uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
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uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr);
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uint32_t (*error)(struct ADIv5_DP_s *dp);
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uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW,
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uint16_t addr, uint32_t value);
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void (*abort)(struct ADIv5_DP_s *dp, uint32_t abort);
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union {
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jtag_dev_t *dev;
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uint8_t fault;
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};
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} ADIv5_DP_t;
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static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr)
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{
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return dp->dp_read(dp, addr);
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}
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static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp)
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{
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return dp->error(dp);
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}
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static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW,
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uint16_t addr, uint32_t value)
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{
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return dp->low_access(dp, RnW, addr, value);
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}
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static inline void adiv5_dp_abort(struct ADIv5_DP_s *dp, uint32_t abort)
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{
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return dp->abort(dp, abort);
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}
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typedef struct ADIv5_AP_s {
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int refcnt;
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ADIv5_DP_t *dp;
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uint8_t apsel;
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uint32_t idr;
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uint32_t cfg;
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uint32_t base;
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uint32_t csw;
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} ADIv5_AP_t;
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void adiv5_dp_init(ADIv5_DP_t *dp);
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void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
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ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
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void adiv5_dp_ref(ADIv5_DP_t *dp);
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void adiv5_ap_ref(ADIv5_AP_t *ap);
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void adiv5_dp_unref(ADIv5_DP_t *dp);
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void adiv5_ap_unref(ADIv5_AP_t *ap);
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void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
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uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr);
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void adiv5_jtag_dp_handler(jtag_dev_t *dev);
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void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
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void adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len);
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void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
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size_t len, enum align align);
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#endif
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