mirror of https://github.com/rusefi/bldc.git
513 lines
15 KiB
C
513 lines
15 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2017-2018 Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements STM32H7 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* Refereces:
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* ST doc - RM0433
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* Reference manual - STM32H7x3 advanced ARM®-based 32-bit MCUs Rev.3
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*/
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#include "general.h"
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#include "target.h"
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#include "target_internal.h"
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#include "cortexm.h"
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static bool stm32h7_cmd_erase_mass(target *t);
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/* static bool stm32h7_cmd_option(target *t, int argc, char *argv[]); */
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static bool stm32h7_uid(target *t);
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static bool stm32h7_crc(target *t);
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static bool stm32h7_cmd_psize(target *t, int argc, char *argv[]);
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const struct command_s stm32h7_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32h7_cmd_erase_mass,
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"Erase entire flash memory"},
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/* {"option", (cmd_handler)stm32h7_cmd_option,
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"Manipulate option bytes"},*/
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{"psize", (cmd_handler)stm32h7_cmd_psize,
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"Configure flash write parallelism: (x8|x16|x32|x64(default))"},
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{"uid", (cmd_handler)stm32h7_uid, "Print unique device ID"},
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{"crc", (cmd_handler)stm32h7_crc, "Print CRC of both banks"},
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{NULL, NULL, NULL}
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};
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr,
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size_t len);
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static int stm32h7_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static const char stm32h74_driver_str[] = "STM32H74x";
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enum stm32h7_regs
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{
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FLASH_ACR = 0x00,
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FLASH_KEYR = 0x04,
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FLASH_OPTKEYR = 0x08,
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FLASH_CR = 0x0c,
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FLASH_SR = 0x10,
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FLASH_CCR = 0x14,
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FLASH_OPTCR = 0x18,
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FLASH_OPTSR_CUR = 0x1C,
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FLASH_OPTSR = 0x20,
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FLASH_CRCCR = 0x50,
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FLASH_CRCDATA = 0x5C,
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};
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/* Flash Program and Erase Controller Register Map */
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#define H7_IWDG_BASE 0x58004c00
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#define FPEC1_BASE 0x52002000
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#define FPEC2_BASE 0x52002100
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_WBNE (1 << 1)
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#define FLASH_SR_QW (1 << 2)
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#define FLASH_SR_CRC_BUSY (1 << 3)
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#define FLASH_SR_EOP (1 << 16)
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#define FLASH_SR_WRPERR (1 << 17)
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#define FLASH_SR_PGSERR (1 << 18)
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#define FLASH_SR_STRBERR (1 << 19)
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#define FLASH_SR_INCERR (1 << 21)
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#define FLASH_SR_OPERR (1 << 22)
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#define FLASH_SR_OPERR (1 << 22)
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#define FLASH_SR_RDPERR (1 << 23)
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#define FLASH_SR_RDSERR (1 << 24)
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#define FLASH_SR_SNECCERR (1 << 25)
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#define FLASH_SR_DBERRERR (1 << 26)
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#define FLASH_SR_ERROR_READ (FLASH_SR_RDPERR | FLASH_SR_RDSERR | \
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FLASH_SR_SNECCERR |FLASH_SR_DBERRERR)
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#define FLASH_SR_ERROR_MASK ( \
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FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \
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FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_ERROR_READ)
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#define FLASH_CR_LOCK (1 << 0)
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#define FLASH_CR_PG (1 << 1)
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#define FLASH_CR_SER (1 << 2)
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#define FLASH_CR_BER (1 << 3)
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#define FLASH_CR_PSIZE8 (0 << 4)
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#define FLASH_CR_PSIZE16 (1 << 4)
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#define FLASH_CR_PSIZE32 (2 << 4)
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#define FLASH_CR_PSIZE64 (3 << 4)
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#define FLASH_CR_FW (1 << 6)
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#define FLASH_CR_START (1 << 7)
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#define FLASH_CR_SNB_1 (1 << 8)
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#define FLASH_CR_SNB (3 << 8)
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#define FLASH_CR_CRC_EN (1 << 15)
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTSR_IWDG1_SW (1 << 4)
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#define FLASH_CRCCR_ALL_BANK (1 << 7)
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#define FLASH_CRCCR_START_CRC (1 << 16)
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#define FLASH_CRCCR_CLEAN_CRC (1 << 17)
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#define FLASH_CRCCR_CRC_BURST_3 (3 << 20)
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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#define OPTKEY1 0x08192A3B
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#define OPTKEY2 0x4C5D6E7F
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#define DBGMCU_IDCODE 0x5c001000
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/* Access via 0xe00e1000 does not show device! */
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#define DBGMCU_CR (DBGMCU_IDCODE + 4)
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#define DBGSLEEP_D1 (1 << 0)
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#define DBGSTOP_D1 (1 << 1)
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#define DBGSTBY_D1 (1 << 2)
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#define DBGSTOP_D3 (1 << 7)
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#define DBGSTBY_D3 (1 << 8)
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#define D1DBGCKEN (1 << 21)
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#define D3DBGCKEN (1 << 22)
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#define FLASH_SIZE_REG 0x1ff1e880
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#define BANK1_START 0x08000000
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#define NUM_SECTOR_PER_BANK 8
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#define FLASH_SECTOR_SIZE 0x20000
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#define BANK2_START 0x08100000
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enum ID_STM32H7 {
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ID_STM32H74x = 0x450,
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};
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struct stm32h7_flash {
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struct target_flash f;
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enum align psize;
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uint32_t regbase;
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};
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static void stm32h7_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize)
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{
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struct stm32h7_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = blocksize;
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f->erase = stm32h7_flash_erase;
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f->write = stm32h7_flash_write;
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f->buf_size = 2048;
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f->erased = 0xff;
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sf->regbase = FPEC1_BASE;
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if (addr >= BANK2_START)
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sf->regbase = FPEC2_BASE;
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sf->psize = ALIGN_DWORD;
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target_add_flash(t, f);
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}
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static bool stm32h7_attach(target *t)
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{
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if (!cortexm_attach(t))
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return false;
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/* RM0433 Rev 4 is not really clear, what bits are needed.
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* Set all possible relevant bits for now. */
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uint32_t dbgmcu_cr = target_mem_read32(t, DBGMCU_CR);
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t->target_storage = dbgmcu_cr;
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target_mem_write32(t, DBGMCU_CR, DBGSLEEP_D1 | D1DBGCKEN);
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/* If IWDG runs as HARDWARE watchdog (44.3.4) erase
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* will be aborted by the Watchdog and erase fails!
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* Setting IWDG_KR to 0xaaaa does not seem to help!*/
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uint32_t optsr = target_mem_read32(t, FPEC1_BASE + FLASH_OPTSR);
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if (!(optsr & FLASH_OPTSR_IWDG1_SW))
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tc_printf(t, "Hardware IWDG running. Expect failure. Set IWDG1_SW!");
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uint32_t flashsize = target_mem_read32(t, FLASH_SIZE_REG);
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flashsize &= 0xffff;
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if (flashsize == 128) { /* H750 has only 128 kByte!*/
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stm32h7_add_flash(t, 0x8000000, FLASH_SECTOR_SIZE, FLASH_SECTOR_SIZE);
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} else {
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stm32h7_add_flash(t, 0x8000000, 0x100000, FLASH_SECTOR_SIZE);
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stm32h7_add_flash(t, 0x8100000, 0x100000, FLASH_SECTOR_SIZE);
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}
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return true;
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}
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static void stm32h7_detach(target *t)
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{
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target_mem_write32(t, DBGMCU_CR, t->target_storage);
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cortexm_detach(t);
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}
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bool stm32h7_probe(target *t)
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{
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ADIv5_AP_t *ap = cortexm_ap(t);
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uint32_t idcode = (ap->dp->targetid >> 16) & 0xfff;
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if (idcode == ID_STM32H74x) {
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t->idcode = idcode;
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t->driver = stm32h74_driver_str;
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t->attach = stm32h7_attach;
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t->detach = stm32h7_detach;
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target_add_commands(t, stm32h7_cmd_list, stm32h74_driver_str);
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target_add_ram(t, 0x00000000, 0x10000); /* ITCM Ram, 64 k */
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target_add_ram(t, 0x20000000, 0x20000); /* DTCM Ram, 128 k */
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target_add_ram(t, 0x24000000, 0x80000); /* AXI Ram, 512 k */
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target_add_ram(t, 0x30000000, 0x20000); /* AHB SRAM1, 128 k */
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target_add_ram(t, 0x32000000, 0x20000); /* AHB SRAM2, 128 k */
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target_add_ram(t, 0x34000000, 0x08000); /* AHB SRAM3, 32 k */
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target_add_ram(t, 0x38000000, 0x01000); /* AHB SRAM4, 32 k */
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return true;
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}
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return false;
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}
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static bool stm32h7_flash_unlock(target *t, uint32_t addr)
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{
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uint32_t regbase = FPEC1_BASE;
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if (addr >= BANK2_START) {
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regbase = FPEC2_BASE;
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}
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while(target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_BSY) {
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if(target_check_error(t))
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return false;
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}
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK) {
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tc_printf(t, "Error 0x%08lx", sr & FLASH_SR_ERROR_MASK);
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target_mem_write32(t, regbase + FLASH_CCR, sr & FLASH_SR_ERROR_MASK);
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return false;
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}
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if (target_mem_read32(t, regbase + FLASH_CR) & FLASH_CR_LOCK) {
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/* Enable FLASH controller access */
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target_mem_write32(t, regbase + FLASH_KEYR, KEY1);
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target_mem_write32(t, regbase + FLASH_KEYR, KEY2);
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}
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if (target_mem_read32(t, regbase + FLASH_CR) & FLASH_CR_LOCK)
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return false;
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else
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return true;
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}
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr,
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size_t len)
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{
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target *t = f->t;
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struct stm32h7_flash *sf = (struct stm32h7_flash *)f;
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if (stm32h7_flash_unlock(t, addr) == false)
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return -1;
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/* We come out of reset with HSI 64 MHz. Adapt FLASH_ACR.*/
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target_mem_write32(t, sf->regbase + FLASH_ACR, 0);
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addr &= (NUM_SECTOR_PER_BANK * FLASH_SECTOR_SIZE) - 1;
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int start_sector = addr / FLASH_SECTOR_SIZE;
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int end_sector = (addr + len - 1) / FLASH_SECTOR_SIZE;
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enum align psize = ((struct stm32h7_flash *)f)->psize;
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uint32_t sr;
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while (start_sector <= end_sector) {
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uint32_t cr = (psize * FLASH_CR_PSIZE16) | FLASH_CR_SER |
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(start_sector * FLASH_CR_SNB_1);
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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cr |= FLASH_CR_START;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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DEBUG(" started cr %08" PRIx32 " sr %08" PRIx32 "\n",
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target_mem_read32(t, sf->regbase + FLASH_CR),
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target_mem_read32(t, sf->regbase + FLASH_SR));
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do {
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sr = target_mem_read32(t, sf->regbase + FLASH_SR);
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if (target_check_error(t)) {
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DEBUG("stm32h7_flash_erase: comm failed\n");
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return -1;
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}
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// target_mem_write32(t, H7_IWDG_BASE, 0x0000aaaa);
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}while (sr & (FLASH_SR_QW | FLASH_SR_BSY));
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG("stm32h7_flash_erase: error, sr: %08" PRIx32 "\n", sr);
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return -1;
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}
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start_sector++;
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}
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return 0;
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}
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static int stm32h7_flash_write(struct target_flash *f, target_addr dest,
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const void *src, size_t len)
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{
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target *t = f->t;
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struct stm32h7_flash *sf = (struct stm32h7_flash *)f;
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enum align psize = sf->psize;
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if (stm32h7_flash_unlock(t, dest) == false)
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return -1;
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uint32_t cr = psize * FLASH_CR_PSIZE16;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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cr |= FLASH_CR_PG;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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/* does H7 stall?*/
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uint32_t sr_reg = sf->regbase + FLASH_SR;
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uint32_t sr;
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target_mem_write(t, dest, src, len);
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while ((sr = target_mem_read32(t, sr_reg)) & FLASH_SR_BSY) {
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if(target_check_error(t)) {
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DEBUG("stm32h7_flash_write: BSY comm failed\n");
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return -1;
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}
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}
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG("stm32h7_flash_write: error sr %08" PRIx32 "\n", sr);
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return -1;
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}
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/* Close write windows.*/
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target_mem_write32(t, sf->regbase + FLASH_CR, 0);
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return 0;
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}
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/* Both banks are erased in parallel.*/
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static bool stm32h7_cmd_erase(target *t, int bank_mask)
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{
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// const char spinner[] = "|/-\\";
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// int spinindex = 0;
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bool do_bank1 = bank_mask & 1, do_bank2 = bank_mask & 2;
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uint32_t cr;
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bool result = false;
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enum align psize = ALIGN_DWORD;
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for (struct target_flash *f = t->flash; f; f = f->next) {
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if (f->write == stm32h7_flash_write) {
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psize = ((struct stm32h7_flash *)f)->psize;
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}
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}
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cr = (psize * FLASH_CR_PSIZE16) | FLASH_CR_BER | FLASH_CR_START;
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/* Flash mass erase start instruction */
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if (do_bank1) {
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if (stm32h7_flash_unlock(t, BANK1_START) == false) {
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DEBUG("ME: Unlock bank1 failed\n");
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goto done;
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}
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uint32_t regbase = FPEC1_BASE;
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/* BER and start can be merged (3.3.10).*/
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target_mem_write32(t, regbase + FLASH_CR, cr);
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DEBUG("ME bank1 started\n");
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}
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if (do_bank2) {
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if (stm32h7_flash_unlock(t, BANK2_START) == false) {
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DEBUG("ME: Unlock bank2 failed\n");
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goto done;
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}
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uint32_t regbase = FPEC2_BASE;
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/* BER and start can be merged (3.3.10).*/
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target_mem_write32(t, regbase + FLASH_CR, cr);
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DEBUG("ME bank2 started\n");
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}
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/* Read FLASH_SR to poll for QW bit */
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if (do_bank1) {
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uint32_t regbase = FPEC1_BASE;
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while (target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_QW) {
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// target_mem_write32(t, H7_IWDG_BASE, 0x0000aaaa);
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// tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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DEBUG("ME bank1: comm failed\n");
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goto done;
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}
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platform_delay(1); // Don't block thread.
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}
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}
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if (do_bank2) {
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uint32_t regbase = FPEC2_BASE;
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while (target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_QW) {
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// target_mem_write32(t, H7_IWDG_BASE 0x0000aaaa);
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// tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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DEBUG("ME bank2: comm failed\n");
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goto done;
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}
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platform_delay(1); // Don't block thread.
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}
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}
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if (do_bank1) {
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/* Check for error */
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uint32_t regbase = FPEC1_BASE;
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG("ME bank1: sr %" PRIx32 "\n", sr);
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goto done;
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}
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}
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if (do_bank2) {
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/* Check for error */
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uint32_t regbase = FPEC2_BASE;
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG("ME bank2: sr %" PRIx32 "\n", sr);
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goto done;
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}
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}
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result = true;
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done:
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tc_printf(t, "\n");
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return result;
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}
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static bool stm32h7_cmd_erase_mass(target *t)
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{
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tc_printf(t, "Erasing flash... This may take a few seconds. ");
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return stm32h7_cmd_erase(t, 3);
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}
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/* Print the Unique device ID.
|
|
* Can be reused for other STM32 devices With uid as parameter.
|
|
*/
|
|
static bool stm32h7_uid(target *t)
|
|
{
|
|
uint32_t uid = 0x1ff1e800;
|
|
int i;
|
|
tc_printf(t, "0x");
|
|
for (i = 0; i < 12; i = i + 4) {
|
|
uint32_t val = target_mem_read32(t, uid + i);
|
|
tc_printf(t, "%02X", (val >> 24) & 0xff);
|
|
tc_printf(t, "%02X", (val >> 16) & 0xff);
|
|
tc_printf(t, "%02X", (val >> 8) & 0xff);
|
|
tc_printf(t, "%02X", (val >> 0) & 0xff);
|
|
}
|
|
tc_printf(t, "\n");
|
|
return true;
|
|
}
|
|
static int stm32h7_crc_bank(target *t, uint32_t bank)
|
|
{
|
|
uint32_t regbase = FPEC1_BASE;
|
|
if (bank >= BANK2_START)
|
|
regbase = FPEC2_BASE;
|
|
|
|
if (stm32h7_flash_unlock(t, bank) == false)
|
|
return -1;
|
|
uint32_t cr = FLASH_CR_CRC_EN;
|
|
target_mem_write32(t, regbase + FLASH_CR, cr);
|
|
uint32_t crccr= FLASH_CRCCR_CRC_BURST_3 |
|
|
FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_ALL_BANK;
|
|
target_mem_write32(t, regbase + FLASH_CRCCR, crccr);
|
|
target_mem_write32(t, regbase + FLASH_CRCCR, crccr | FLASH_CRCCR_START_CRC);
|
|
uint32_t sr;
|
|
while ((sr = target_mem_read32(t, regbase + FLASH_SR)) & FLASH_SR_CRC_BUSY) {
|
|
if(target_check_error(t)) {
|
|
DEBUG("CRC bank %d: comm failed\n", (bank < BANK2_START) ? 1 : 2);
|
|
return -1;
|
|
}
|
|
if (sr & FLASH_SR_ERROR_READ) {
|
|
DEBUG("CRC bank %d: error sr %08" PRIx32 "\n",
|
|
(bank < BANK2_START) ? 1 : 2, sr);
|
|
return -1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static bool stm32h7_crc(target *t)
|
|
{
|
|
if (stm32h7_crc_bank(t, BANK1_START) ) return false;
|
|
uint32_t crc1 = target_mem_read32(t, FPEC1_BASE + FLASH_CRCDATA);
|
|
if (stm32h7_crc_bank(t, BANK2_START) ) return false;
|
|
uint32_t crc2 = target_mem_read32(t, FPEC1_BASE + FLASH_CRCDATA);
|
|
tc_printf(t, "CRC: bank1 0x%08lx, bank2 0x%08lx\n", crc1, crc2);
|
|
return true;
|
|
}
|
|
static bool stm32h7_cmd_psize(target *t, int argc, char *argv[])
|
|
{
|
|
if (argc == 1) {
|
|
enum align psize = ALIGN_DWORD;
|
|
for (struct target_flash *f = t->flash; f; f = f->next) {
|
|
if (f->write == stm32h7_flash_write) {
|
|
psize = ((struct stm32h7_flash *)f)->psize;
|
|
}
|
|
}
|
|
tc_printf(t, "Flash write parallelism: %s\n",
|
|
psize == ALIGN_DWORD ? "x64" :
|
|
psize == ALIGN_WORD ? "x32" :
|
|
psize == ALIGN_HALFWORD ? "x16" : "x8");
|
|
} else {
|
|
enum align psize;
|
|
if (!strcmp(argv[1], "x8")) {
|
|
psize = ALIGN_BYTE;
|
|
} else if (!strcmp(argv[1], "x16")) {
|
|
psize = ALIGN_HALFWORD;
|
|
} else if (!strcmp(argv[1], "x32")) {
|
|
psize = ALIGN_WORD;
|
|
} else if (!strcmp(argv[1], "x64")) {
|
|
psize = ALIGN_DWORD;
|
|
} else {
|
|
tc_printf(t, "usage: monitor psize (x8|x16|x32|x64)\n");
|
|
return false;
|
|
}
|
|
for (struct target_flash *f = t->flash; f; f = f->next) {
|
|
if (f->write == stm32h7_flash_write) {
|
|
((struct stm32h7_flash *)f)->psize = psize;
|
|
}
|
|
}
|
|
}
|
|
return true;
|
|
}
|