From ff378b19d9f37f47adaa0b9cd3686860b6701e8e Mon Sep 17 00:00:00 2001 From: denis Date: Thu, 12 Mar 2015 16:54:57 +0300 Subject: [PATCH] first public commit --- .cproject | 52 + .gitignore | 12 + .project | 95 + Makefile | 232 ++ STM32F407xG.ld | 158 ++ board/ST_STM32F4_DISCOVERY/board.c | 108 + board/ST_STM32F4_DISCOVERY/board.h | 1296 +++++++++ board/ST_STM32F4_DISCOVERY/board.mk | 5 + board/ST_STM32F4_DISCOVERY/cfg/board.chcfg | 1192 +++++++++ chconf.h | 531 ++++ ext/.gitignore | 1 + ext/build_data.lua.diff | 12 + ext/ch_lua.c | 134 + ext/elua_chibios_mod.c | 50 + ext/ext.mk | 262 ++ ext/mmcfs.c | 359 +++ .../board_stm32f4chibios.h.dis | 169 ++ ext/platform_chibios/build_config.lua | 21 + ext/platform_chibios/conf.lua | 53 + ext/platform_chibios/cpu_chibios_cpu.h | 46 + ext/platform_chibios/platform.c | 214 ++ ext/platform_chibios/platform_conf.h.dis | 98 + ext/platform_chibios/platform_generic.h | 12 + ext/platform_chibios/stacks.h | 9 + ext/platform_chibios/type.h | 18 + ext/stm32f4chibios.lua | 24 + halconf.h | 319 +++ iar/ch.ewp | 2371 +++++++++++++++++ iar/ch.eww | 10 + iar/ch.icf | 39 + keil/ch.uvproj | 980 +++++++ main.c | 349 +++ mcuconf.h | 288 ++ readme.md | 31 + readme.txt | 30 + rules.mk | 257 ++ usbcfg.c | 314 +++ usbcfg.h | 25 + 38 files changed, 10176 insertions(+) create mode 100644 .cproject create mode 100644 .gitignore create mode 100644 .project create mode 100644 Makefile create mode 100644 STM32F407xG.ld create mode 100644 board/ST_STM32F4_DISCOVERY/board.c create mode 100644 board/ST_STM32F4_DISCOVERY/board.h create mode 100644 board/ST_STM32F4_DISCOVERY/board.mk create mode 100644 board/ST_STM32F4_DISCOVERY/cfg/board.chcfg create mode 100644 chconf.h create mode 100644 ext/.gitignore create mode 100644 ext/build_data.lua.diff create mode 100644 ext/ch_lua.c create mode 100644 ext/elua_chibios_mod.c create mode 100644 ext/ext.mk create mode 100644 ext/mmcfs.c create mode 100644 ext/platform_chibios/board_stm32f4chibios.h.dis create mode 100644 ext/platform_chibios/build_config.lua create mode 100644 ext/platform_chibios/conf.lua create mode 100644 ext/platform_chibios/cpu_chibios_cpu.h create mode 100644 ext/platform_chibios/platform.c create mode 100644 ext/platform_chibios/platform_conf.h.dis create mode 100644 ext/platform_chibios/platform_generic.h create mode 100644 ext/platform_chibios/stacks.h create mode 100644 ext/platform_chibios/type.h create mode 100644 ext/stm32f4chibios.lua create mode 100644 halconf.h create mode 100644 iar/ch.ewp create mode 100644 iar/ch.eww create mode 100644 iar/ch.icf create mode 100644 keil/ch.uvproj create mode 100644 main.c create mode 100644 mcuconf.h create mode 100644 readme.md create mode 100644 readme.txt create mode 100644 rules.mk create mode 100644 usbcfg.c create mode 100644 usbcfg.h diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..4c0ec41 --- /dev/null +++ b/.cproject @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3187b87 --- /dev/null +++ b/.gitignore @@ -0,0 +1,12 @@ +build/ +.dep/ +*.hex +*.elf +*.dfu +*.o +*.obj +*.exe +*.bin +*.pyc +*.map +build.log \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..20074f5 --- /dev/null +++ b/.project @@ -0,0 +1,95 @@ + + + ARMCM4-STM32F407-DISCOVERY-MEMS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_STM32F4_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..85b9802 --- /dev/null +++ b/Makefile @@ -0,0 +1,232 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# +BUILDDIR = build + +# Compiler options here. +ifeq ($(USE_OPT),) + #~ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +#~ ifeq ($(USE_VERBOSE_COMPILE),) + #~ USE_VERBOSE_COMPILE = no +#~ endif +USE_VERBOSE_COMPILE = yes + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + #requred for elua + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch +CHIBIOSLUA ?= $(shell pwd) +# Imported source files and paths +CHIBIOS = $(CHIBIOSLUA)/../ChibiOS +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +#LDSCRIPT= $(PORTLD)/STM32F407xG.ld +LDSCRIPT= STM32F407xG.ld +#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/devices_lib/accel/lis302dl.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + usbcfg.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) $(EXT_ASMSRC) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOSLUA) \ + $(EXT_INC) \ + $(CHIBIOS)/os/various/devices_lib/accel \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DELUA_CPU_HEADER="\"cpu_chibios_cpu.h\"" -DELUA_BOARD_HEADER="\"board_stm32f4chibios.h\"" -DUSE_GIT_REVISION -DELUA_CPU=CHIBIOS_CPU -DELUA_BOARD=STM32F4CHIBIOS -DELUA_PLATFORM=CHIBIOS -D__BUFSIZ__=128 -DELUA_CPU_CHIBIOS_CPU -DELUA_BOARD_STM32F4CHIBIOS -DELUA_PLATFORM_CHIBIOS -DLUA_PACK_VALUE -DELUA_ENDIAN_LITTLE -DLUA_OPTIMIZE_MEMORY=2 -DFORCHIBIOS_CPU +DDEFS += -DUSE_MULTIPLE_ALLOCATOR -DCHPRINTF_USE_FLOAT=TRUE +#~ DDEFS += -DUSE_SIMPLE_ALLOCATOR + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lm + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +#RULESPATH = $(CHIBIOS)/os/ports/GCC/ARMCMx +#include $(RULESPATH)/rules.mk +include $(CHIBIOSLUA)/ext/ext.mk + +include ./rules.mk + + +######## resource usage show ################ diff --git a/STM32F407xG.ld b/STM32F407xG.ld new file mode 100644 index 0000000..efc7aca --- /dev/null +++ b/STM32F407xG.ld @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x0400; /*chibios kernel stack*/ +__process_stack_size__ = 0x8000; /* 4096???? main thread stack*/ + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 64k + elua : org = 0x20010000, len = 64k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + PROVIDE(stext = .); + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + . = ALIGN(4); + _etext = .; + _sidata = _etext; + PROVIDE(etext = .); + _fini = . ; + *(.fini) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/board/ST_STM32F4_DISCOVERY/board.c b/board/ST_STM32F4_DISCOVERY/board.c new file mode 100644 index 0000000..99569f6 --- /dev/null +++ b/board/ST_STM32F4_DISCOVERY/board.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/board/ST_STM32F4_DISCOVERY/board.h b/board/ST_STM32F4_DISCOVERY/board.h new file mode 100644 index 0000000..9004163 --- /dev/null +++ b/board/ST_STM32F4_DISCOVERY/board.h @@ -0,0 +1,1296 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F4-Discovery" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + +/* + * MCU type as defined in the ST header. + */ +#define STM32F40_41xxx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_LRCK 4 +#define GPIOA_SPC 5 +#define GPIOA_SDO 6 +#define GPIOA_SDI 7 +#define GPIOA_PIN8 8 +#define GPIOA_VBUS_FS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_SCL 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_SDA 9 +#define GPIOB_CLK_IN 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_OTG_FS_POWER_ON 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PDM_OUT 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_MCLK 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_SCLK 10 +#define GPIOC_PIN11 11 +#define GPIOC_SDIN 12 +#define GPIOC_PIN13 13 +#define GPIOC_PIN14 14 +#define GPIOC_PIN15 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_RESET 4 +#define GPIOD_OVER_CURRENT 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_LED4 12 +#define GPIOD_LED3 13 +#define GPIOD_LED5 14 +#define GPIOD_LED6 15 + +#define GPIOE_INT1 0 +#define GPIOE_INT2 1 +#define GPIOE_PIN2 2 +#define GPIOE_CS_SPI 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_PIN10 10 +#define GPIOG_PIN11 11 +#define GPIOG_PIN12 12 +#define GPIOG_PIN13 13 +#define GPIOG_PIN14 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - LRCK (alternate 6). + * PA5 - SPC (alternate 5). + * PA6 - SDO (alternate 5). + * PA7 - SDI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \ + PIN_OSPEED_100M(GPIOA_PIN1) | \ + PIN_OSPEED_100M(GPIOA_PIN2) | \ + PIN_OSPEED_100M(GPIOA_PIN3) | \ + PIN_OSPEED_100M(GPIOA_LRCK) | \ + PIN_OSPEED_50M(GPIOA_SPC) | \ + PIN_OSPEED_50M(GPIOA_SDO) | \ + PIN_OSPEED_50M(GPIOA_SDI) | \ + PIN_OSPEED_100M(GPIOA_PIN8) | \ + PIN_OSPEED_100M(GPIOA_VBUS_FS) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_100M(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPC) | \ + PIN_PUPDR_FLOATING(GPIOA_SDO) | \ + PIN_PUPDR_FLOATING(GPIOA_SDI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_LRCK) | \ + PIN_ODR_HIGH(GPIOA_SPC) | \ + PIN_ODR_HIGH(GPIOA_SDO) | \ + PIN_ODR_HIGH(GPIOA_SDI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_LRCK, 6) | \ + PIN_AFIO_AF(GPIOA_SPC, 5) | \ + PIN_AFIO_AF(GPIOA_SDO, 5) | \ + PIN_AFIO_AF(GPIOA_SDI, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - SDA (alternate 4). + * PB10 - CLK_IN (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_SCL) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOB_SDA) | \ + PIN_MODE_INPUT(GPIOB_CLK_IN) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ + PIN_OSPEED_100M(GPIOB_PIN1) | \ + PIN_OSPEED_100M(GPIOB_PIN2) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_100M(GPIOB_PIN4) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_SCL) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_PIN8) | \ + PIN_OSPEED_100M(GPIOB_SDA) | \ + PIN_OSPEED_100M(GPIOB_CLK_IN) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ + PIN_OSPEED_100M(GPIOB_PIN12) | \ + PIN_OSPEED_100M(GPIOB_PIN13) | \ + PIN_OSPEED_100M(GPIOB_PIN14) | \ + PIN_OSPEED_100M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_SCL) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_SDA) | \ + PIN_ODR_HIGH(GPIOB_CLK_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PDM_OUT (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - MCLK (alternate 6). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SCLK (alternate 6). + * PC11 - PIN11 (input pullup). + * PC12 - SDIN (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PDM_OUT) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOC_MCLK) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_SCLK) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIN) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_100M(GPIOC_PIN1) | \ + PIN_OSPEED_100M(GPIOC_PIN2) | \ + PIN_OSPEED_100M(GPIOC_PDM_OUT) | \ + PIN_OSPEED_100M(GPIOC_PIN4) | \ + PIN_OSPEED_100M(GPIOC_PIN5) | \ + PIN_OSPEED_100M(GPIOC_PIN6) | \ + PIN_OSPEED_100M(GPIOC_MCLK) | \ + PIN_OSPEED_100M(GPIOC_PIN8) | \ + PIN_OSPEED_100M(GPIOC_PIN9) | \ + PIN_OSPEED_100M(GPIOC_SCLK) | \ + PIN_OSPEED_100M(GPIOC_PIN11) | \ + PIN_OSPEED_100M(GPIOC_SDIN) | \ + PIN_OSPEED_100M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_PIN14) | \ + PIN_OSPEED_100M(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_MCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_SCLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIN) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PDM_OUT) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_MCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_SCLK) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_SDIN) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_MCLK, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_SCLK, 6) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_SDIN, 6) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - RESET (output pushpull maximum). + * PD5 - OVER_CURRENT (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_OUTPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ + PIN_OSPEED_100M(GPIOD_PIN1) | \ + PIN_OSPEED_100M(GPIOD_PIN2) | \ + PIN_OSPEED_100M(GPIOD_PIN3) | \ + PIN_OSPEED_100M(GPIOD_RESET) | \ + PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_100M(GPIOD_PIN6) | \ + PIN_OSPEED_100M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_PIN8) | \ + PIN_OSPEED_100M(GPIOD_PIN9) | \ + PIN_OSPEED_100M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_PIN11) | \ + PIN_OSPEED_100M(GPIOD_LED4) | \ + PIN_OSPEED_100M(GPIOD_LED3) | \ + PIN_OSPEED_100M(GPIOD_LED5) | \ + PIN_OSPEED_100M(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_RESET) | \ + PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_LED4) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_LED5) | \ + PIN_PUPDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_RESET) | \ + PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_LOW(GPIOD_LED4) | \ + PIN_ODR_LOW(GPIOD_LED3) | \ + PIN_ODR_LOW(GPIOD_LED5) | \ + PIN_ODR_LOW(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_RESET, 0) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_LED4, 0) | \ + PIN_AFIO_AF(GPIOD_LED3, 0) | \ + PIN_AFIO_AF(GPIOD_LED5, 0) | \ + PIN_AFIO_AF(GPIOD_LED6, 0)) + +/* + * GPIOE setup: + * + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). + * PE2 - PIN2 (input floating). + * PE3 - CS_SPI (output pushpull maximum). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ + PIN_MODE_INPUT(GPIOE_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \ + PIN_OSPEED_100M(GPIOE_INT2) | \ + PIN_OSPEED_100M(GPIOE_PIN2) | \ + PIN_OSPEED_100M(GPIOE_CS_SPI) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_PIN8) | \ + PIN_OSPEED_100M(GPIOE_PIN9) | \ + PIN_OSPEED_100M(GPIOE_PIN10) | \ + PIN_OSPEED_100M(GPIOE_PIN11) | \ + PIN_OSPEED_100M(GPIOE_PIN12) | \ + PIN_OSPEED_100M(GPIOE_PIN13) | \ + PIN_OSPEED_100M(GPIOE_PIN14) | \ + PIN_OSPEED_100M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \ + PIN_PUPDR_FLOATING(GPIOE_INT2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \ + PIN_ODR_HIGH(GPIOE_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_CS_SPI) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input floating). + * PF1 - PIN1 (input floating). + * PF2 - PIN2 (input floating). + * PF3 - PIN3 (input floating). + * PF4 - PIN4 (input floating). + * PF5 - PIN5 (input floating). + * PF6 - PIN6 (input floating). + * PF7 - PIN7 (input floating). + * PF8 - PIN8 (input floating). + * PF9 - PIN9 (input floating). + * PF10 - PIN10 (input floating). + * PF11 - PIN11 (input floating). + * PF12 - PIN12 (input floating). + * PF13 - PIN13 (input floating). + * PF14 - PIN14 (input floating). + * PF15 - PIN15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ + PIN_OSPEED_100M(GPIOF_PIN1) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_PIN4) | \ + PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_PIN9) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_PIN11) | \ + PIN_OSPEED_100M(GPIOF_PIN12) | \ + PIN_OSPEED_100M(GPIOF_PIN13) | \ + PIN_OSPEED_100M(GPIOF_PIN14) | \ + PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input floating). + * PG1 - PIN1 (input floating). + * PG2 - PIN2 (input floating). + * PG3 - PIN3 (input floating). + * PG4 - PIN4 (input floating). + * PG5 - PIN5 (input floating). + * PG6 - PIN6 (input floating). + * PG7 - PIN7 (input floating). + * PG8 - PIN8 (input floating). + * PG9 - PIN9 (input floating). + * PG10 - PIN10 (input floating). + * PG11 - PIN11 (input floating). + * PG12 - PIN12 (input floating). + * PG13 - PIN13 (input floating). + * PG14 - PIN14 (input floating). + * PG15 - PIN15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ + PIN_OSPEED_100M(GPIOG_PIN1) | \ + PIN_OSPEED_100M(GPIOG_PIN2) | \ + PIN_OSPEED_100M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_PIN4) | \ + PIN_OSPEED_100M(GPIOG_PIN5) | \ + PIN_OSPEED_100M(GPIOG_PIN6) | \ + PIN_OSPEED_100M(GPIOG_PIN7) | \ + PIN_OSPEED_100M(GPIOG_PIN8) | \ + PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_PIN10) | \ + PIN_OSPEED_100M(GPIOG_PIN11) | \ + PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_PIN13) | \ + PIN_OSPEED_100M(GPIOG_PIN14) | \ + PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/board/ST_STM32F4_DISCOVERY/board.mk b/board/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 0000000..eb47aa2 --- /dev/null +++ b/board/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY diff --git a/board/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/board/ST_STM32F4_DISCOVERY/cfg/board.chcfg new file mode 100644 index 0000000..fd1a569 --- /dev/null +++ b/board/ST_STM32F4_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1192 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + STMicroelectronics STM32F4-Discovery + ST_STM32F4_DISCOVERY + + STM32F40_41xxx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/chconf.h b/chconf.h new file mode 100644 index 0000000..f943ea8 --- /dev/null +++ b/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/ext/.gitignore b/ext/.gitignore new file mode 100644 index 0000000..4f714ba --- /dev/null +++ b/ext/.gitignore @@ -0,0 +1 @@ +elua/ diff --git a/ext/build_data.lua.diff b/ext/build_data.lua.diff new file mode 100644 index 0000000..3b109b0 --- /dev/null +++ b/ext/build_data.lua.diff @@ -0,0 +1,12 @@ +--- ./build_data.lua.orig 2014-11-10 15:58:33.000000000 +0300 ++++ ./build_data.lua 2014-11-08 08:43:51.000000000 +0300 +@@ -114,7 +114,8 @@ + stm32f4 = { cpus = { 'STM32F401RE', 'STM32F407VG', 'STM32F407ZG' }, arch = 'cortexm' }, + avr32 = { cpus = { 'AT32UC3A0128', 'AT32UC3A0256', 'AT32UC3A0512', 'AT32UC3B0256' }, arch = 'avr32' }, + lpc24xx = { cpus = { 'LPC2468' }, arch = 'arm' }, +- lpc17xx = { cpus = { 'LPC1768' }, arch = 'cortexm' } ++ lpc17xx = { cpus = { 'LPC1768' }, arch = 'cortexm' }, ++ chibios = { cpus = { 'CHIBIOS_CPU' }, arch = 'cortexm' } + } + + -- Returns the platform of a given CPU diff --git a/ext/ch_lua.c b/ext/ch_lua.c new file mode 100644 index 0000000..f2393ca --- /dev/null +++ b/ext/ch_lua.c @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include "platform.h" +#include "romfs.h" +#include "xmodem.h" +#include "elua/inc/shell.h" +#include "elua/src/lua/lua.h" +#include "elua/src/lua/lauxlib.h" +#include "elua/src/lua/lualib.h" +#include "term.h" +#include "platform_conf.h" +#include "elua_rfs.h" +#ifdef ELUA_SIMULATOR +#include "hostif.h" +#endif + +// Validate eLua configuratin options +#include "validate.h" + +#include "mmcfs.h" +#include "romfs.h" +#include "semifs.h" + +// Define here your autorun/boot files, +// in the order you want eLua to search for them +const char *boot_order[] = { +#if defined(BUILD_MMCFS) + "/mmc/autorun.lua", + "/mmc/autorun.lc", +#endif +#if defined(BUILD_WOFS) + "/wo/autorun.lua", + "/wo/autorun.lc", +#endif +#if defined(BUILD_ROMFS) + "/rom/autorun.lua", + "/rom/autorun.lc", +#endif +#if defined(BUILD_SEMIFS) + "/semi/autorun.lua", + "/semi/autorun.lc", +#endif +}; + +extern char etext[]; + +#ifdef ELUA_BOOT_RPC +void boot_rpc( void ) +{ + lua_State *L = lua_open(); + luaL_openlibs(L); /* open libraries */ + + // Set up UART for 8N1 w/ adjustable baud rate + platform_uart_setup( RPC_UART_ID, RPC_UART_SPEED, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 ); + + // Start RPC Server + lua_getglobal( L, "rpc" ); + lua_getfield( L, -1, "server" ); + lua_pushnumber( L, RPC_UART_ID ); + lua_pushnumber( L, RPC_TIMER_ID ); + lua_pcall( L, 2, 0, 0 ); +} +#endif // #ifdef ELUA_BOOT_RPC + +// **************************************************************************** +// Program entry point + +//~ int main( void ) +int main_lua( void ) +{ + int i; + FILE* fp; + + // Initialize platform first + if( platform_init() != PLATFORM_OK ) + { + // This should never happen + while( 1 ); + } + + // Initialize device manager + dm_init(); + + // Register the ROM filesystem + romfs_init(); + + // Register the MMC filesystem + //~ mmcfs_init(); + + // Register the Semihosting filesystem + semifs_init(); + + // Register the remote filesystem + remotefs_init(); + + // Search for autorun files in the defined order and execute the 1st if found + for( i = 0; i < sizeof( boot_order ) / sizeof( *boot_order ); i++ ) + { + //elua/src/newlib/stubs.c _open_r + if( ( fp = fopen( boot_order[ i ], "r" ) ) != NULL ) + { + fclose( fp ); + char* lua_argv[] = { (char *)"lua", (char *)boot_order[i], NULL }; + lua_main( 2, lua_argv ); + break; // autoruns only the first found + } + } + +#ifdef ELUA_BOOT_RPC + boot_rpc(); +#else + printf("hello\n\r"); + // Run the shell + if( shell_init() == 0 ) + { + // Start Lua directly + char* lua_argv[] = { (char *)"lua", NULL }; + lua_main( 1, lua_argv ); + } + else + shell_start(); +#endif // #ifdef ELUA_BOOT_RPC + +#ifdef ELUA_SIMULATOR + hostif_exit(0); + return 0; +#else + while( 1 ); +#endif + +} + diff --git a/ext/elua_chibios_mod.c b/ext/elua_chibios_mod.c new file mode 100644 index 0000000..3f08f10 --- /dev/null +++ b/ext/elua_chibios_mod.c @@ -0,0 +1,50 @@ +#include "lua.h" +#include "lualib.h" +#include "lauxlib.h" +#include "platform.h" +#include "lrotable.h" +#include "platform_conf.h" +#include "auxmods.h" + + + +//Lua: SleepMilliseconds(millsec) +static int sleep_milliseconds( lua_State *L ) +{ + unsigned milli; + + milli = luaL_checkinteger( L, 1 ); + chThdSleepMilliseconds(milli); + return 0; +} +//Lua: SleepSeconds(sec) +static int sleep_senonds( lua_State *L ) +{ + unsigned sec; + + sec = luaL_checkinteger( L, 1 ); + chThdSleepSeconds(sec); + return 0; +} + +#define MIN_OPT_LEVEL 2 +#include "lrodefs.h" + +// Module function map +const LUA_REG_TYPE thd_map[] = +{ + { LSTRKEY( "SleepMilliseconds" ), LFUNCVAL( sleep_milliseconds ) }, + { LSTRKEY( "SleepSeconds" ), LFUNCVAL( sleep_milliseconds ) }, + { LNILKEY, LNILVAL } +}; + +LUALIB_API int luaopen_thd( lua_State *L ) +{ + LREGISTER( L, "thd", thd_map ); +} + +// Add the module to the module table. Do *NOT* terminate this with a NULL entry +// The linker script does it for you. +//~ _ELUA_MODTAB = { + //~ { "ch", luaopen_chibios } +//~ }; diff --git a/ext/ext.mk b/ext/ext.mk new file mode 100644 index 0000000..33b66b2 --- /dev/null +++ b/ext/ext.mk @@ -0,0 +1,262 @@ +ELUA=$(CHIBIOSLUA)/ext/elua + +ELUA_SRC_CSRC = $(ELUA)/src/buf.c \ + $(ELUA)/src/common.c \ + $(ELUA)/src/common_fs.c \ + $(ELUA)/src/common_tmr.c \ + $(ELUA)/src/common_uart.c \ + $(ELUA)/src/dlmalloc.c \ + $(ELUA)/src/elua_adc.c \ + $(ELUA)/src/elua_int.c \ + $(ELUA)/src/elua_uip.c \ + $(ELUA)/src/eluarpc.c \ + $(ELUA)/src/linenoise.c \ + $(ELUA)/src/romfs.c \ + $(ELUA)/src/salloc.c \ + $(ELUA)/src/semifs.c \ + $(ELUA)/src/xmodem.c \ + $(ELUA)/src/luarpc_elua_uart.c \ + $(ELUA)/src/term.c + + +ELUA_LUA_CSRC = $(ELUA)/src/lua/lapi.c \ + $(ELUA)/src/lua/lauxlib.c \ + $(ELUA)/src/lua/lbaselib.c \ + $(ELUA)/src/lua/lcode.c \ + $(ELUA)/src/lua/ldblib.c \ + $(ELUA)/src/lua/ldebug.c \ + $(ELUA)/src/lua/ldo.c \ + $(ELUA)/src/lua/ldump.c \ + $(ELUA)/src/lua/legc.c \ + $(ELUA)/src/lua/lfunc.c \ + $(ELUA)/src/lua/lgc.c \ + $(ELUA)/src/lua/linit.c \ + $(ELUA)/src/lua/liolib.c \ + $(ELUA)/src/lua/llex.c \ + $(ELUA)/src/lua/lmathlib.c \ + $(ELUA)/src/lua/lmem.c \ + $(ELUA)/src/lua/loadlib.c \ + $(ELUA)/src/lua/lobject.c \ + $(ELUA)/src/lua/lopcodes.c \ + $(ELUA)/src/lua/loslib.c \ + $(ELUA)/src/lua/lparser.c \ + $(ELUA)/src/lua/lrotable.c \ + $(ELUA)/src/lua/lstate.c \ + $(ELUA)/src/lua/lstring.c \ + $(ELUA)/src/lua/lstrlib.c \ + $(ELUA)/src/lua/ltable.c \ + $(ELUA)/src/lua/ltablib.c \ + $(ELUA)/src/lua/ltm.c \ + $(ELUA)/src/lua/lua.c \ + $(ELUA)/src/lua/lundump.c \ + $(ELUA)/src/lua/lvm.c \ + $(ELUA)/src/lua/lzio.c + + +ELUA_MODULES_CSRC = $(ELUA)/src/modules/adc.c \ + $(ELUA)/src/modules/bit.c \ + $(ELUA)/src/modules/bitarray.c \ + $(ELUA)/src/modules/can.c \ + $(ELUA)/src/modules/cpu.c \ + $(ELUA)/src/modules/elua.c \ + $(ELUA)/src/modules/i2c.c \ + $(ELUA)/src/modules/lpack.c \ + $(ELUA)/src/modules/luarpc.c \ + $(ELUA)/src/modules/net.c \ + $(ELUA)/src/modules/pd.c \ + $(ELUA)/src/modules/pio.c \ + $(ELUA)/src/modules/pwm.c \ + $(ELUA)/src/modules/spi.c \ + $(ELUA)/src/modules/tmr.c \ + $(ELUA)/src/modules/uart.c \ + $(ELUA)/src/modules/term.c + + +ELUA_NEWLIB_CSRC = $(ELUA)/src/newlib/devman.c \ + $(ELUA)/src/newlib/genstd.c \ + $(ELUA)/src/newlib/stdtcp.c \ + $(ELUA)/src/newlib/stubs.c + + +ELUA_REMOTEFS_CSRC = $(ELUA)/src/remotefs/client.c \ + $(ELUA)/src/remotefs/elua_os_io.c \ + $(ELUA)/src/remotefs/elua_rfs.c \ + $(ELUA)/src/remotefs/remotefs.c + + +ELUA_SHELL_CSRC = $(ELUA)/src/shell/shell.c \ + $(ELUA)/src/shell/shell_adv_cp_mv.c \ + $(ELUA)/src/shell/shell_adv_rm.c \ + $(ELUA)/src/shell/shell_cat.c \ + $(ELUA)/src/shell/shell_help.c \ + $(ELUA)/src/shell/shell_ls.c \ + $(ELUA)/src/shell/shell_lua.c \ + $(ELUA)/src/shell/shell_mkdir.c \ + $(ELUA)/src/shell/shell_recv.c \ + $(ELUA)/src/shell/shell_ver.c \ + $(ELUA)/src/shell/shell_wofmt.c \ + $(ELUA)/src/shell/vi.c + + +ELUA_uIP_CSRC = $(ELUA)/src/uip/uip_arp.c \ + $(ELUA)/src/uip/uip.c \ + $(ELUA)/src/uip/uiplib.c \ + $(ELUA)/src/uip/dhcpc.c \ + $(ELUA)/src/uip/psock.c \ + $(ELUA)/src/uip/resolv.c \ + $(ELUA)/src/uip/uip-neighbor.c + + +ELUA_PLATFORM1_CSRC = $(CHIBIOSLUA)/ext/platform_chibios/platform.c + +ELUA_PLATFORM2_CSRC = $(ELUA)/src/platform/arm_cortex_interrupts.c + +ELUA_EXT_CSRC = $(CHIBIOSLUA)/ext/elua_chibios_mod.c \ + $(CHIBIOSLUA)/ext/elua_zumo.c \ + $(CHIBIOSLUA)/ext/ch_lua.c + +# $(ELUA)/src/platform/arm_utils.s \ + +ELUA_FATFS_CSRC = $(ELUA)/src/fatfs/ccsbcs.c \ + $(ELUA)/src/fatfs/ff.c + + +#ELUA_ALL_CSRC = $(ELUA_EXT_CSRC) $(ELUA_SRC_CSRC) $(ELUA_FATFS_CSRC) $(ELUA_LUA_CSRC) $(ELUA_MODULES_CSRC) $(ELUA_NEWLIB_CSRC) $(ELUA_REMOTEFS_CSRC) $(ELUA_SHELL_CSRC) $(ELUA_uIP_CSRC) $(ELUA_PLATFORM1_CSRC) $(ELUA_PLATFORM2_CSRC) + + +ELUA_SRC_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_SRC_CSRC:.c=.o.elua_src))) +ELUA_LUA_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_LUA_CSRC:.c=.o.elua_lua))) +ELUA_MODULES_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_MODULES_CSRC:.c=.o.elua_modules))) +ELUA_NEWLIB_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_NEWLIB_CSRC:.c=.o.elua_newlib))) +ELUA_REMOTEFS_OBJS= $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_REMOTEFS_CSRC:.c=.o.elua_remotefs))) +ELUA_SHELL_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_SHELL_CSRC:.c=.o.elua_shell))) +ELUA_uIP_OBJS = $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_uIP_CSRC:.c=.o.elua_uip))) +ELUA_PLATFORM_OBJS= $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_PLATFORM_CSRC:.c=.o.elua_platform))) +ELUA_FATFS_OBJS= $(addprefix $(BUILDDIR)/obj/, $(notdir $(ELUA_FATFS_CSRC:.c=.o.elua_fatfs))) +ELUA_EXT_OBJS= $(BUILDDIR)/obj/ch_lua.o.ext $(BUILDDIR)/obj/elua_chibios_mod.o.ext $(BUILDDIR)/obj/elua_zumo.o.ext $(BUILDDIR)/obj/platform.o.PLATFORM1 $(BUILDDIR)/obj/arm_cortex_interrupts.o.PLATFORM2 + + +EXT_INC = $(CHIBIOSLUA)/ext \ + $(ELUA)/inc \ + $(ELUA)/inc/newlib \ + $(CHIBIOSLUA)/ext/platform_chibios \ + $(ELUA)/src/lua \ + $(ELUA)/src/modules \ + $(ELUA)/boards/headers \ + $(ELUA)/inc/remotefs + +EXT_ASMSRC = $(ELUA)/src/platform/cortex_utils.s + +# $(shell ls $(ELUA)/src/platform/chibios 2>/dev/null || ln -s $(CHIBIOSLUA)/ext/platform_chibios $(ELUA)/src/platform/chibios 2>/dev/null) \ +# $(shell ls $(ELUA)/src/boards/headers/board_stm32f4chibios.h 2>/dev/null || ln -s $(CHIBIOSLUA)/ext/platform_chibios/board_stm32f4chibios.h $(ELUA)/src/boards/headers/board_stm32f4chibios.h 2>/dev/null) \ + +EXT_PREPROCESS_SHELL=$(warning EXT_PREPROCESS_SHELL) \ + $(shell ln -s $(CHIBIOSLUA)/ext/stm32f4chibios.lua $(ELUA)/boards/known/stm32f4chibios.lua 2>/dev/null) \ + $(shell (cd ${ELUA} ; patch -N <$(CHIBIOSLUA)/ext/build_data.lua.diff ; ./build_elua.lua board=stm32f4chibios config_only=true; ./build_elua.lua board=stm32f4chibios) >>./build.log 2>&1) + +#main link with rules.mk +ELUA_ALL_OBJS= $(EXT_PREPROCESS_SHELL) $(ELUA_EXT_OBJS) $(ELUA_SRC_OBJS) $(ELUA_LUA_OBJS) $(ELUA_MODULES_OBJS) $(ELUA_NEWLIB_OBJS) $(ELUA_REMOTEFS_OBJS) $(ELUA_SHELL_OBJS) $(ELUA_uIP_OBJS) $(ELUA_PLATFORM_OBJS) + +$(BUILDDIR)/obj/%.o.elua_src : $(ELUA)/src/%.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( +#include +#include +#include "ioctl.h" +#include + +#include "platform_conf.h" +#ifdef BUILD_MMCFS +#include "ff.h" +//~ #include "diskio.h" +#include +#include +#include + +#define MMCFS_MAX_FDS 4 +static FIL mmcfs_fd_table[ MMCFS_MAX_FDS ]; +static int mmcfs_num_fd; + +extern void elua_mmc_init( void ); + +#ifndef MMCFS_NUM_CARDS +#define NUM_CARDS 1 +#else +#define NUM_CARDS MMCFS_NUM_CARDS +#endif + +// Data structures used by FatFs +static FATFS mmc_fs[ NUM_CARDS ]; +static FIL mmc_fileObject; +//static DIR mmc_dir; +//static FILINFO mmc_fileInfo; +typedef struct +{ + DIR *dir; + struct dm_dirent *pdm; +} MMCFS_DIRENT_DATA; + +static int mmcfs_find_empty_fd( void ) +{ + int i; + + for (i = 0; i < MMCFS_MAX_FDS; i ++) + if (mmcfs_fd_table[i].fs == NULL) + return i; + return -1; +} + +static int mmcfs_open_r( struct _reent *r, const char *path, int flags, int mode, void *pdata ) +{ + int fd; + int mmc_mode; + char *mmc_pathBuf; + int drv_num = *( int* )pdata; + + if (mmcfs_num_fd == MMCFS_MAX_FDS) + { + r->_errno = ENFILE; + return -1; + } + + // Default to top directory if none given + if (strchr(path, '/') == NULL) + asprintf( &mmc_pathBuf, "%d:/%s", drv_num, path ); + else + asprintf( &mmc_pathBuf, "%d:%s", drv_num, path ); + if( mmc_pathBuf == NULL ) + { + r->_errno = ENOMEM; + return -1; + } + + // Scrub binary flag, if defined +#ifdef O_BINARY + flags &= ~O_BINARY; +#endif + +#if _FS_READONLY + if ((flags & O_ACCMODE) != O_RDONLY) + { + r->_errno = EROFS; + free( mmc_pathBuf ); + return -1; + } + mmc_mode = FA_OPEN_EXISTING & FA_READ; +#else + // Translate fcntl.h mode to FatFs mode (by jcwren@jcwren.com) + if (((flags & (O_CREAT | O_TRUNC)) == (O_CREAT | O_TRUNC)) && (flags & (O_RDWR | O_WRONLY))) + mmc_mode = FA_CREATE_ALWAYS; + else if ((flags & (O_CREAT | O_EXCL)) == (O_CREAT | O_EXCL)) + mmc_mode = FA_OPEN_EXISTING; + else if ((flags & O_CREAT) == O_CREAT) + mmc_mode = FA_OPEN_ALWAYS; + else if ((flags == O_RDONLY) || (flags == O_WRONLY) || (flags == O_RDWR)) + mmc_mode = FA_OPEN_EXISTING; + else + { + r->_errno = EINVAL; + free( mmc_pathBuf ); + return -1; + } + + if ((flags & O_ACCMODE) == O_RDONLY) + mmc_mode |= FA_READ; + else if ((flags & O_ACCMODE) == O_WRONLY) + mmc_mode |= FA_WRITE; + else if ((flags & O_ACCMODE) == O_RDWR) + mmc_mode |= (FA_READ | FA_WRITE); + else + { + r->_errno = EINVAL; + free( mmc_pathBuf ); + return -1; + } +#endif // _FS_READONLY + + // Open the file for reading + if (f_open(&mmc_fileObject, mmc_pathBuf, mmc_mode) != FR_OK) + { + r->_errno = ENOENT; + free( mmc_pathBuf ); + return -1; + } + + if (mode & O_APPEND) + mmc_fileObject.fptr = mmc_fileObject.fsize; + fd = mmcfs_find_empty_fd(); + memcpy(mmcfs_fd_table + fd, &mmc_fileObject, sizeof(FIL)); + mmcfs_num_fd ++; + free( mmc_pathBuf ); + return fd; +} + +static int mmcfs_close_r( struct _reent *r, int fd, void *pdata ) +{ + FIL* pFile = mmcfs_fd_table + fd; + + f_close( pFile ); + memset(pFile, 0, sizeof(FIL)); + mmcfs_num_fd --; + return 0; +} + +static _ssize_t mmcfs_write_r( struct _reent *r, int fd, const void* ptr, size_t len, void *pdata ) +{ +#if _FS_READONLY + { + r->_errno = EIO; + return -1; + } +#else + UINT bytesWritten; + + if (f_write(mmcfs_fd_table + fd, ptr, len, &bytesWritten) != FR_OK) + { + r->_errno = EIO; + return -1; + } + + return (_ssize_t) bytesWritten; +#endif // _FS_READONLY +} + +static _ssize_t mmcfs_read_r( struct _reent *r, int fd, void* ptr, size_t len, void *pdata ) +{ + UINT bytesRead; + + if (f_read(mmcfs_fd_table + fd, ptr, len, &bytesRead) != FR_OK) + { + r->_errno = EIO; + return -1; + } + + return (_ssize_t) bytesRead; +} + +// lseek +static off_t mmcfs_lseek_r( struct _reent *r, int fd, off_t off, int whence, void *pdata ) +{ + FIL* pFile = mmcfs_fd_table + fd; + u32 newpos = 0; + + switch( whence ) + { + case SEEK_SET: + // seek from beginning of file + newpos = off; + break; + + case SEEK_CUR: + // seek from current position + newpos = pFile->fptr + off; + break; + + case SEEK_END: + // seek from end of file + newpos = pFile->fsize + off; + break; + + default: + return -1; + } + if (f_lseek (pFile, newpos) != FR_OK) + return -1; + return newpos; +} + +// opendir +static void* mmcfs_opendir_r( struct _reent *r, const char* dname, void *pdata ) +{ + void* res = NULL; + MMCFS_DIRENT_DATA *pd = ( MMCFS_DIRENT_DATA* )malloc( sizeof( MMCFS_DIRENT_DATA ) ); + int drv_num = *( int* )pdata; + char *pname = NULL; + + if( !pd ) + return NULL; + memset( pd, 0, sizeof( MMCFS_DIRENT_DATA ) ); + if( ( pd->dir = ( DIR* )malloc( sizeof( DIR ) ) ) == NULL ) + goto out; + if( ( pd->pdm = ( struct dm_dirent* )malloc( sizeof( struct dm_dirent ) ) ) == NULL ) + goto out; + if( !dname || strlen( dname ) == 0 ) + asprintf( &pname, "%d:/", drv_num ); + else + asprintf( &pname, "%d:%s", drv_num, dname ); + res = f_opendir( pd->dir, pname ) != FR_OK ? NULL : pd; +out: + if( res == NULL ) + { + if( pd->dir ) + free( pd->dir ); + if( pd->pdm ) + free( pd->pdm ); + free( pd ); + } + if( pname ) + free( pname ); + return res; +} + +// readdir +extern char dm_shared_fname[ DM_MAX_FNAME_LENGTH + 1 ]; +static struct dm_dirent* mmcfs_readdir_r( struct _reent *r, void *d, void *pdata ) +{ + MMCFS_DIRENT_DATA *pd = ( MMCFS_DIRENT_DATA* )d; + DIR *pdir = pd->dir; + FILINFO mmc_file_info; + struct dm_dirent* pent = pd->pdm; + char *fn; +#if _USE_LFN + static char lfn[_MAX_LFN * (_DF1S ? 2 : 1) + 1]; + mmc_file_info.lfname = lfn; + mmc_file_info.lfsize = sizeof(lfn); +#endif + + while( 1 ) // loop until we get a file, error, or end of directory + { + if( f_readdir( pdir, &mmc_file_info ) != FR_OK ) // return NULL on read error + return NULL; + if( mmc_file_info.fname[ 0 ] == '\0' ) // return NULL when listing is done + return NULL; + break; + } +#if _USE_LFN + fn = *mmc_file_info.lfname ? mmc_file_info.lfname : mmc_file_info.fname; +#else + fn = mmc_file_info.fname; +#endif + if( ( mmc_file_info.fattrib & AM_DIR ) != 0 ) // if we have a file, exit loop + pent->flags = DM_DIRENT_FLAG_DIR; + else + pent->flags = 0; + strncpy( dm_shared_fname, fn, DM_MAX_FNAME_LENGTH ); + pent->fname = dm_shared_fname; + pent->fsize = mmc_file_info.fsize; + pent->ftime = mmc_file_info.ftime; + return pent; +} + +// closedir +static int mmcfs_closedir_r( struct _reent *r, void *d, void *pdata ) +{ + MMCFS_DIRENT_DATA *pd = ( MMCFS_DIRENT_DATA* )d; + + free( pd->dir ); + free( pd->pdm ); + free( pd ); + return 0; +} + +static int mmcfs_mkdir_r( struct _reent *r, const char *name, mkdir_mode_t mode, void *pdata ) +{ + return f_mkdir( name ); +} + +static int mmcfs_unlink_r( struct _reent *r, const char *fname, void *pdata ) +{ + return f_unlink( fname ); +} + +static int mmcfs_rename_r( struct _reent *r, const char *oldname, const char *newname, void *pdata ) +{ + return f_rename( oldname, newname ); +} + +// MMC device descriptor structure +static const DM_DEVICE mmcfs_device = +{ + mmcfs_open_r, // open + mmcfs_close_r, // close + mmcfs_write_r, // write + mmcfs_read_r, // read + mmcfs_lseek_r, // lseek + mmcfs_opendir_r, // opendir + mmcfs_readdir_r, // readdir + mmcfs_closedir_r, // closedir + NULL, // getaddr + mmcfs_mkdir_r, // mkdir + mmcfs_unlink_r, // unlink + mmcfs_unlink_r, // rmdir + mmcfs_rename_r // rename +}; + +int mmcfs_init() +{ + //~ elua_mmc_init(); +#if NUM_CARDS == 1 + static int cid = 0; + // A single MMCFS + if ( f_mount( 0, mmc_fs ) != FR_OK ) + return DM_ERR_INIT; + return dm_register( "/mmc", &cid, &mmcfs_device ); +#else // #if NUM_CARDS == 1 + int i; + static char names[ NUM_CARDS ][ 6 ]; + static int ids[ NUM_CARDS ]; + + // [TODO] add more error checking! + for( i = 0; i < NUM_CARDS; i ++ ) + if( f_mount( i, mmc_fs + i ) == FR_OK ) + { + ids[ i ] = i; + sprintf( names[ i ], "/mmc%d", i ); + dm_register( names[ i ], ids + i, &mmcfs_device ); + } + return DM_OK; +#endif // #if NUM_CARDS == 1 +} + +#else // #ifdef BUILD_MMCFS + +int mmcfs_init() +{ + return dm_register( NULL, NULL, NULL ); +} + +#endif // BUILD_MMCFS diff --git a/ext/platform_chibios/board_stm32f4chibios.h.dis b/ext/platform_chibios/board_stm32f4chibios.h.dis new file mode 100644 index 0000000..61634f4 --- /dev/null +++ b/ext/platform_chibios/board_stm32f4chibios.h.dis @@ -0,0 +1,169 @@ +// Lua board configuration file, automatically generated + +#ifndef __GENERATED_STM32F4CHIBIOS_H__ +#define __GENERATED_STM32F4CHIBIOS_H__ + +//////////////////////////////////////////////////////////////////////////////// +// Configuration for section 'components' + +// Configuration for element 'romfs' +#define BUILD_ROMFS + +// Configuration for element 'xmodem' +#define CON_FLOW_TYPE PLATFORM_UART_FLOW_NONE +#define CON_UART_SPEED 115200 +#define CON_TIMER_ID 0 +#define CON_UART_ID 0 +#define BUILD_XMODEM + +// Configuration for element 'rpc' +#define RPC_UART_SPEED 115200 +#define RPC_TIMER_ID PLATFORM_TIMER_SYS_ID +#define RPC_UART_ID 0 +#define BUILD_RPC + +// Configuration for element 'term' +#define TERM_LINES 25 +#define TERM_COLS 80 +#define BUILD_TERM + +// Configuration for element 'sercon' +#define BUILD_CON_GENERIC + +// Configuration for element 'shell' +#define BUILD_SHELL + +//////////////////////////////////////////////////////////////////////////////// +// Configuration for section 'config' + +// Configuration for element 'ram' +#define MEM_START_ADDRESS { ( u32 )( INTERNAL_RAM1_FIRST_FREE ) } +#define MEM_END_ADDRESS { ( u32 )( INTERNAL_RAM1_LAST_FREE ) } + +// Configuration for element 'vtmr' +#define VTMR_FREQ_HZ 1 +#define VTMR_NUM_TIMERS 0 + +/////////////////////////////////////////////////////////////////////////////// +// Static sanity checks and additional defines + +#if defined( ELUA_BOOT_RPC ) && !defined( BUILD_RPC ) +#define BUILD_RPC +#endif + +#if defined( BUILD_LUA_INT_HANDLERS ) || defined( BUILD_C_INT_HANDLERS ) + #define BUILD_INT_HANDLERS + + #ifndef INT_TMR_MATCH + #define INT_TMR_MATCH ELUA_INT_INVALID_INTERRUPT + #endif +#endif // #if defined( BUILD_LUA_INT_HANDLERS ) || defined( BUILD_C_INT_HANDLERS ) + +#ifndef VTMR_NUM_TIMERS +#define VTMR_NUM_TIMERS 0 +#endif // #ifndef VTMR_NUM_TIMERS + +#ifndef SERMUX_FLOW_TYPE +#define SERMUX_FLOW_TYPE PLATFORM_UART_FLOW_NONE +#endif + +#ifndef CON_FLOW_TYPE +#define CON_FLOW_TYPE PLATFORM_UART_FLOW_NONE +#endif + +#ifndef CON_TIMER_ID +#define CON_TIMER_ID PLATFORM_TIMER_SYS_ID +#endif + +#ifndef RFS_FLOW_TYPE +#define RFS_FLOW_TYPE PLATFORM_UART_FLOW_NONE +#endif + +#ifdef ELUA_BOOT_RPC + #ifndef RPC_UART_ID + #define RPC_UART_ID CON_UART_ID + #endif + + #ifndef RPC_TIMER_ID + #define RPC_TIMER_ID PLATFORM_TIMER_SYS_ID + #endif + + #ifndef RPC_UART_SPEED + #define RPC_UART_SPEED CON_UART_SPEED + #endif +#endif // #ifdef ELUA_BOOT_RPC + +#if ( defined( BUILD_RFS ) || defined( BUILD_SERMUX ) || defined( CON_BUF_SIZE ) || defined ( CDC_BUF_SIZE ) ) && !defined( BUF_ENABLE_UART ) +#define BUF_ENABLE_UART +#endif + +#if defined( ADC_BUF_SIZE ) && !defined( BUF_ENABLE_ADC ) +#define BUF_ENABLE_ADC +#endif + +#ifndef CPU_FREQUENCY +#define CPU_FREQUENCY 0 +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Module configuration + +#define PLATFORM_MODULES_LINE +#define MODULE_ELUA_LINE _ROM( AUXLIB_ELUA, luaopen_elua, elua_map ) + +#if ( NUM_PIO > 0 ) +#define MODULE_PIO_LINE _ROM( AUXLIB_PIO, luaopen_pio, pio_map ) +#else +#define MODULE_PIO_LINE +#warning Unable to include generic module 'pio' in the image +#endif + +#if ( NUM_UART > 0 ) +#define MODULE_UART_LINE _ROM( AUXLIB_UART, luaopen_uart, uart_map ) +#else +#define MODULE_UART_LINE +#warning Unable to include generic module 'uart' in the image +#endif + +#define MODULE_LUA_TABLE_LINE _ROM( LUA_TABLIBNAME, luaopen_table, tab_funcs ) +#define MODULE_LUA_DEBUG_LINE _ROM( LUA_DBLIBNAME, luaopen_debug, dblib ) + +#if defined( BUILD_RPC ) +#define MODULE_RPC_LINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map ) +#else +#define MODULE_RPC_LINE +#warning Unable to include generic module 'rpc' in the image +#endif + +#define MODULE_LUA_MATH_LINE _ROM( LUA_MATHLIBNAME, luaopen_math, math_map ) + +#if defined( BUILD_TERM ) +#define MODULE_TERM_LINE _ROM( AUXLIB_TERM, luaopen_term, term_map ) +#else +#define MODULE_TERM_LINE +#warning Unable to include generic module 'term' in the image +#endif + +#define MODULE_LUA_STRING_LINE _ROM( LUA_STRLIBNAME, luaopen_string, strlib ) +#define MODULE_LUA_CO_LINE _ROM( LUA_COLIBNAME, luaopen_dummy, co_funcs ) +#define MODULE_PD_LINE _ROM( AUXLIB_PD, luaopen_pd, pd_map ) + +#define LUA_PLATFORM_LIBS_ROM\ + PLATFORM_MODULES_LINE\ + MODULE_ELUA_LINE\ + MODULE_PIO_LINE\ + MODULE_UART_LINE\ + MODULE_LUA_TABLE_LINE\ + MODULE_LUA_DEBUG_LINE\ + MODULE_RPC_LINE\ + MODULE_LUA_MATH_LINE\ + MODULE_TERM_LINE\ + MODULE_LUA_STRING_LINE\ + MODULE_LUA_CO_LINE\ + MODULE_PD_LINE + +#define LUA_LIBS_NOLTR\ + { LUA_IOLIBNAME, luaopen_io },\ + { LUA_LOADLIBNAME, luaopen_package },\ + +#endif // #ifndef __GENERATED_STM32F4CHIBIOS_H__ diff --git a/ext/platform_chibios/build_config.lua b/ext/platform_chibios/build_config.lua new file mode 100644 index 0000000..3c85c13 --- /dev/null +++ b/ext/platform_chibios/build_config.lua @@ -0,0 +1,21 @@ +-- This is the platform specific board configuration file +-- It is used by the generic board configuration system (config/) + +module( ..., package.seeall ) + +-- Add specific components to the 'components' table +function add_platform_components( t ) +end + +-- Add specific configuration to the 'configs' table +function add_platform_configs( t ) +end + +-- Return an array of all the available platform modules for the given cpu +function get_platform_modules( board, cpu ) + return { + thd = { lib = '"thd"' }, + zumo = { lib = '"zumo"' } + } +end + diff --git a/ext/platform_chibios/conf.lua b/ext/platform_chibios/conf.lua new file mode 100644 index 0000000..7848d8b --- /dev/null +++ b/ext/platform_chibios/conf.lua @@ -0,0 +1,53 @@ + +local utils = require "utils.utils" +local sf = string.format + +addi( sf( '%s', os.getenv( "INCDIR" ) or '' ) ) +--~ addlib( { 'c','gcc','m' } ) + +-- Configuration file for the LPC288x backend + + +specific_files = "platform.c" + +local ldscript = "" + + +-- Prepend with path +specific_files = utils.prepend_path( specific_files, sf( "src/platform/%s", platform ) ) +specific_files = specific_files .. " src/platform/cortex_utils.s src/platform/arm_cortex_interrupts.c" +--~ ldscript = sf( "src/platform/%s/%s", platform, ldscript ) + +addm{ "FOR" .. comp.cpu:upper(), 'gcc' } + +-- Standard GCC flags +addcf( { '-O0' } ) +addcf( { '-g' } ) +--~ addcf{ '-ffunction-sections', '-fdata-sections', '-fno-strict-aliasing', '-Wall' } +--~ addlf{ '-nostartfiles', '-nostdlib', '-T', ldscript, '-Wl,--gc-sections', '-Wl,--allow-multiple-definition' } +--~ addaf{ '-x', 'assembler-with-cpp', '-Wall' } +--~ addlib{ 'c','gcc','m' } + +-- Special target configuration +local target_flags = { '-mcpu=cortex-m4', '-mthumb','-mfloat-abi=hard', '-mfpu=fpv4-sp-d16' } + +-- Configure general flags for target +addcf( { target_flags, '-mlittle-endian' } ) +addlf( { target_flags, '-Wl,-e,Reset_Handler', '-Wl,-static' } ) +addaf( target_flags ) + +--~ addm( 'CPUMODE_ARM' ) + +addcf( target_flags ) +--~ addlf{ target_flags, '-Wl,-e,HardReset' } +--~ addaf{ target_flags,'-D__ASSEMBLY__' } + +-- Toolset data +tools.chibios = {} + +-- Array of file names that will be checked against the 'prog' target; their absence will force a rebuild +tools.chibios.prog_flist = { output .. ".bin" } + +-- We use 'gcc' as the assembler +toolset.asm = toolset.compile + diff --git a/ext/platform_chibios/cpu_chibios_cpu.h b/ext/platform_chibios/cpu_chibios_cpu.h new file mode 100644 index 0000000..546dc55 --- /dev/null +++ b/ext/platform_chibios/cpu_chibios_cpu.h @@ -0,0 +1,46 @@ +// i386 (Intel) CPU configuration + +#ifndef __CPU_I386_H__ +#define __CPU_I386_H__ + +#include "stacks.h" + +// Number of resources (0 if not available/not implemented) +#define NUM_PIO 5 /*port count*/ +#define NUM_SPI 0 +#define NUM_UART 1 +#define NUM_TIMER 0 +#define NUM_PWM 0 +#define NUM_ADC 0 +#define NUM_CAN 0 + +// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used) +#define CPU_FREQUENCY 0 + +// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...) +#define PIO_PREFIX 'A' +// Pins per port configuration: +// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or +// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array +// Use #define PIO_PINS_PER_PORT 0 if this isn't needed +#define PIO_PINS_PER_PORT 16 + +// Allocator data: define your free memory zones here in two arrays +// (start address and end address) +//~ #define SRAM_ORIGIN 0x20010000 +//~ #define SRAM_SIZE 0x10000 +//~ #define INTERNAL_RAM1_FIRST_FREE end +//~ #define INTERNAL_RAM1_LAST_FREE ( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) +#define INTERNAL_SRAM_BASE 0x20010000 +#define INTERNAL_SRAM_SIZE ( 63 * 1024 ) +#define INTERNAL_RAM1_FIRST_FREE 0x20010000 +#define INTERNAL_RAM1_LAST_FREE ( INTERNAL_SRAM_BASE + INTERNAL_SRAM_SIZE - STACK_SIZE_TOTAL -1 ) +//dlmalloc.h MORECORE -> _sbrk_r (newlib) / elua_sbrk (multiple) -> +// -> platform_get_first_free_ram -> MEM_START_ADDRESS -> INTERNAL_RAM1_FIRST_FREE + +#define BUILD_MMCFS 1 +#define PLATFORM_HAS_SYSTIMER 1 + +//INTERNAL_RAM1_LAST_FREE -> MEM_END_ADDRESS +#endif // #ifndef __CPU_I386_H__ + diff --git a/ext/platform_chibios/platform.c b/ext/platform_chibios/platform.c new file mode 100644 index 0000000..2bedb8f --- /dev/null +++ b/ext/platform_chibios/platform.c @@ -0,0 +1,214 @@ +// Platform-dependent functions + +#include "platform.h" +#include "type.h" +#include "devman.h" +#include "genstd.h" +#include "stacks.h" +#include +#include +#include +#include +#include +//#include "lpc288x.h" +//#include "target.h" +//#include "uart.h" +#include "utils.h" +#include "common.h" +#include "platform_conf.h" +#include "hal.h" + +// **************************************************************************** +// Platform initialization + +int platform_init() +{ + + // Setup PIO, not needed, done in chibios board.h + //pios_init(); + + cmn_platform_init(); + + return PLATFORM_OK; +} + +// **************************************************************************** +// PIO functions +GPIO_TypeDef * const pio_port[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI }; +uint16_t const ignore_pins[] = { 1<<2|1<<3|1<<11|1<<12, /*A2,A3,A11,A12 UART2 RX,TX,GPIOA_OTG_FS_DM,GPIOA_OTG_FS_DP */ + 0,0,0,0,0,0,0,0,0}; + +pio_type platform_pio_op( unsigned port, pio_type pinmask, int op ) +{ + pio_type retval = 1;//ok , 0-error + GPIO_TypeDef * target_port = pio_port[ port ]; + uint16_t new_state = 0xffff; + + switch( op ) + { + case PLATFORM_IO_PORT_SET_VALUE: + palWritePort(target_port,pinmask); + break; + + case PLATFORM_IO_PORT_DIR_OUTPUT: + new_state &= ~(ignore_pins[port]);//exclude some pins + palSetGroupMode(target_port,new_state, 0, PAL_STM32_MODE_OUTPUT | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_MID1 | PAL_STM32_PUDR_FLOATING ); + break; + + case PLATFORM_IO_PORT_DIR_INPUT: + new_state &= ~(ignore_pins[port]);//exclude some pins + palSetGroupMode(target_port,new_state, 0, PAL_STM32_MODE_INPUT | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_MID1 | PAL_STM32_PUDR_FLOATING ); + break; + + case PLATFORM_IO_PORT_GET_VALUE: + retval=palReadPort(target_port); + break; + + case PLATFORM_IO_PIN_GET: + retval=palReadPad(target_port,pinmask); + break; + + case PLATFORM_IO_PIN_SET: + if(ignore_pins[port] & pinmask) + retval=0;//notify user about error + pinmask &= ~(ignore_pins[port]); + palSetPort(target_port,pinmask); + break; + + case PLATFORM_IO_PIN_CLEAR: + if(ignore_pins[port] & pinmask) + retval=0;//notify user about error + pinmask &= ~(ignore_pins[port]); + palClearPort(target_port,pinmask); + break; + + case PLATFORM_IO_PIN_DIR_OUTPUT: + if(ignore_pins[port] & pinmask) + retval=0;//notify user about error + pinmask &= ~(ignore_pins[port]); + palSetGroupMode(target_port,pinmask, 0, PAL_STM32_MODE_OUTPUT); + break; + + case PLATFORM_IO_PIN_DIR_INPUT: + if(ignore_pins[port] & pinmask) + retval=0;//notify user about error + pinmask &= ~(ignore_pins[port]); + palSetGroupMode(target_port,pinmask, 0, PAL_STM32_MODE_INPUT); + break; + + default: + retval = 0; + break; + } + return retval; +} + +// **************************************************************************** +// UART + +u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits ) +{ + ( void )id; + return 0;//uart_init( baud, databits, parity, stopbits ); +} + +void platform_s_uart_send( unsigned id, u8 data ) +{ + sdPutTimeout((SerialDriver*)eLuaSDriver, data,1000/*ticks, TIME_IMMEDIATE - bad idea*/); + //uart_write( data ); +} + +int platform_s_uart_recv( unsigned id, timer_data_type timeout ) +{ + if( timeout == 0 ) + { + // Return data only if already available + return sdGetTimeout((SerialDriver*)eLuaSDriver,TIME_IMMEDIATE); + } + if( timeout == -1 || timeout == STD_INFINITE_TIMEOUT) + { + // Return data only if already available + return sdGetTimeout((SerialDriver*)eLuaSDriver,TIME_INFINITE); + } + return sdGetTimeout((SerialDriver*)eLuaSDriver,timeout); + +} + +int platform_s_uart_set_flow_control( unsigned id, int type ) +{ + return PLATFORM_ERR; +} + +// **************************************************************************** +// Timer + + +// Helper: get timer clock +static u32 platform_timer_get_clock( unsigned id ) +{ + return 0;//MAIN_CLOCK / tmr_prescale[ ( *tmr_ctrl[ id ] >> 2 ) & 0x03 ]; +} + +// Helper: set timer clock +static u32 platform_timer_set_clock( unsigned id, u32 clock ) +{ + return 0;//MAIN_CLOCK / tmr_prescale[ mini ]; +} + +void platform_s_timer_delay( unsigned id, timer_data_type delay_us ) +{ +} + +timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data ) +{ + u32 res = 0; + //~ TIM_TypeDef *ptimer = (TIM_TypeDef*)timer[ id ]; + + data = data; + switch( op ) + { + case PLATFORM_TIMER_OP_START: + //~ TIM_SetCounter( ptimer, 0 ); + res = chTimeNow(); + break; + + case PLATFORM_TIMER_OP_READ: + res = chTimeNow();//TIM_GetCounter( ptimer ); + break; + + case PLATFORM_TIMER_OP_SET_CLOCK: + res = CH_FREQUENCY;//platform_timer_set_clock( id, data ); + break; + + case PLATFORM_TIMER_OP_GET_CLOCK: + res = CH_FREQUENCY;//platform_timer_get_clock( id ); + break; + + case PLATFORM_TIMER_OP_GET_MAX_CNT: + res = 0xFFFFFFFF;//( timer_width[id] == 32 ? 0xFFFFFFFF : 0xFFFF ); + break; + + } + return res; + +} + +u64 platform_timer_sys_raw_read() +{ + return MS2ST(chTimeNow()); +} + +void platform_timer_sys_disable_int() +{ + //~ SysTick->CTRL &= ~( 1 << SysTick_CTRL_TICKINT_Pos ); +} + +void platform_timer_sys_enable_int() +{ + //~ SysTick->CTRL |= 1 << SysTick_CTRL_TICKINT_Pos; +} + +timer_data_type platform_timer_read_sys() +{ + return MS2ST(chTimeNow()); +} diff --git a/ext/platform_chibios/platform_conf.h.dis b/ext/platform_chibios/platform_conf.h.dis new file mode 100644 index 0000000..a2c38bb --- /dev/null +++ b/ext/platform_chibios/platform_conf.h.dis @@ -0,0 +1,98 @@ +// eLua platform configuration + +#ifndef __PLATFORM_CONF_H__ +#define __PLATFORM_CONF_H__ + +#include "auxmods.h" +#include "type.h" +#include "stacks.h" + +#define BUILD_CON_GENERIC +#define BUILD_SHELL +#define BUILD_TERM +#define BUILD_ROMFS +#define BUILD_XMODEM +#define BUILD_LINENOISE + +// ***************************************************************************** +// UART/Timer IDs configuration data (used in main.c) + +#define CON_UART_ID 0 +#define CON_UART_SPEED 115200 +#define TERM_LINES 25 +#define TERM_COLS 80 + +#define PLATFORM_HAS_SYSTIMER + +// ***************************************************************************** +// Auxiliary libraries that will be compiled for this platform + +//~ #define LUA_PLATFORM_LIBS_ROM\ + //~ _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\ + //~ _ROM( AUXLIB_ELUA, luaopen_elua, elua_map )\ + //~ _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\ + //~ _ROM( AUXLIB_PIO, luaopen_pio, pio_map ) + +// ***************************************************************************** +// Configuration data + +#define EGC_INITIAL_MODE 1 + +// Number of resources (0 if not available/not implemented) +//~ #define NUM_PIO 16 +//~ #define NUM_SPI 0 +//~ #define NUM_UART 1 +//~ #define NUM_TIMER 0 +//~ #define NUM_PHYS_TIMER 0 +//~ #define NUM_PWM 0 +//~ #define NUM_ADC 0 +//~ #define NUM_CAN 0 + +// PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...) +//~ #define PIO_PREFIX '0' +// Pins per port configuration: +// #define PIO_PINS_PER_PORT (n) if each port has the same number of pins, or +// #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array +// Use #define PIO_PINS_PER_PORT 0 if this isn't needed +//~ #define PIO_PIN_ARRAY { 16, 16, 16, 16, 8, 12, 7, 0, 0, 0, 0, 0, 0, 0, 14, 12 } + +#define LINENOISE_HISTORY_SIZE_LUA 50 +#define LINENOISE_HISTORY_SIZE_SHELL 10 + +// Interrupt queue size +#define PLATFORM_INT_QUEUE_LOG_SIZE 5 + +// Allocator data: define your free memory zones here in two arrays +// (start address and end address) +//~ #define SRAM_SIZE ( 64 * 1024 ) +//~ #define SRAM_BASE 0x20000000 +//~ #define MEM_START_ADDRESS { ( void* )end } +//~ #define MEM_END_ADDRESS { ( void* )( SRAM_BASE + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) } + +//~ #define CPU_FREQUENCY 120000000 + +#define AUXLIB_CHIBIOS "thd" + +#define LUA_PLATFORM_LIBS_REG \ + {LUA_LOADLIBNAME, luaopen_package },\ + {LUA_TABLIBNAME, luaopen_table },\ + {LUA_IOLIBNAME, luaopen_io },\ + {LUA_OSLIBNAME, luaopen_os},\ + {LUA_STRLIBNAME, luaopen_string },\ + {LUA_MATHLIBNAME, luaopen_math },\ + {LUA_DBLIBNAME, luaopen_debug }, \ + {AUXLIB_CHIBIOS, luaopen_chibios, ch_thread_map} + +#define LUA_PLATFORM_LIBS_ROM\ + _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\ + _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\ + _ROM( AUXLIB_PD, luaopen_pd, pd_map )\ + _ROM( AUXLIB_UART, luaopen_uart, uart_map )\ + _ROM( AUXLIB_TERM, luaopen_term, term_map )\ + _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\ + _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\ + _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\ + _ROM( LUA_MATHLIBNAME, luaopen_math, math_map ) + +#endif // #ifndef __PLATFORM_CONF_H__ + diff --git a/ext/platform_chibios/platform_generic.h b/ext/platform_chibios/platform_generic.h new file mode 100644 index 0000000..d09ac7b --- /dev/null +++ b/ext/platform_chibios/platform_generic.h @@ -0,0 +1,12 @@ +// Platform customization header + +#ifndef __PLATFORM_GENERIC_H__ +#define __PLATFORM_GENERIC_H__ + +#include "ch.h" + +//~ #define PLATFORM_TMR_COUNTS_DOWN +extern BaseSequentialStream *eLuaSDriver; + +#endif // #ifndef __PLATFORM_GENERIC_H__ + diff --git a/ext/platform_chibios/stacks.h b/ext/platform_chibios/stacks.h new file mode 100644 index 0000000..e5f4d51 --- /dev/null +++ b/ext/platform_chibios/stacks.h @@ -0,0 +1,9 @@ +// Stack size definitions + +#ifndef __STACKS_H__ +#define __STACKS_H__ + +#define STACK_SIZE 4096 +#define STACK_SIZE_TOTAL ( STACK_SIZE ) + +#endif diff --git a/ext/platform_chibios/type.h b/ext/platform_chibios/type.h new file mode 100644 index 0000000..fc29fbb --- /dev/null +++ b/ext/platform_chibios/type.h @@ -0,0 +1,18 @@ +#ifndef __TYPE_H__ +#define __TYPE_H__ + +typedef unsigned char BYTE; +typedef unsigned short WORD; +typedef unsigned long DWORD; +typedef unsigned int BOOL; + +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef signed short s16; +typedef unsigned long u32; +typedef signed long s32; +typedef unsigned long long u64; +typedef signed long long s64; + +#endif diff --git a/ext/stm32f4chibios.lua b/ext/stm32f4chibios.lua new file mode 100644 index 0000000..0ce041c --- /dev/null +++ b/ext/stm32f4chibios.lua @@ -0,0 +1,24 @@ +-- STM32F4DISCOVERY build configuration + +return { + cpu = 'CHIBIOS_CPU', + components = { + sercon = { uart = 0, speed = 115200, timer = 0 }, + romfs = true, + --~ shell = true, + advanced_shell = true, + term = { lines = 25, cols = 80 }, + linenoise = { shell_lines = 10, lua_lines = 50 }, + xmodem = true, + rpc = { uart = 0, speed = 115200 } + }, + --~ config = { + --~ ram = { ext_start = { "SDRAM_BASE_ADDR" }, ext_size = { "SDRAM_SIZE" } } + --~ }, + modules = { + --~ generic = { 'pd', 'uart', 'term', 'pack', 'bit', 'elua', 'cpu', 'rpc', 'all_lua' } + generic = { 'pd', 'uart', 'term', 'elua', 'rpc', 'pio', 'all_lua' }, + platform = 'all', + } +} + diff --git a/halconf.h b/halconf.h new file mode 100644 index 0000000..a4766ce --- /dev/null +++ b/halconf.h @@ -0,0 +1,319 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * elua + */ +//~ #define CHIBILUA_SERIAL 1 +#define CHIBILUA_USBSERIAL 1 + + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/iar/ch.ewp b/iar/ch.ewp new file mode 100644 index 0000000..a1239b5 --- /dev/null +++ b/iar/ch.ewp @@ -0,0 +1,2371 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\TIMv1\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\TIMv1\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\nvic.h + + + + various + + devices_lib + + accel + + $PROJ_DIR$\..\..\..\os\various\devices_lib\accel\lis302dl.c + + + $PROJ_DIR$\..\..\..\os\various\devices_lib\accel\lis302dl.h + + + + + $PROJ_DIR$\..\..\..\os\various\chprintf.c + + + $PROJ_DIR$\..\..\..\os\various\chprintf.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/iar/ch.eww b/iar/ch.eww new file mode 100644 index 0000000..f9b3b20 --- /dev/null +++ b/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/iar/ch.icf b/iar/ch.icf new file mode 100644 index 0000000..c0a51f4 --- /dev/null +++ b/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/keil/ch.uvproj b/keil/ch.uvproj new file mode 100644 index 0000000..74460f8 --- /dev/null +++ b/keil/ch.uvproj @@ -0,0 +1,980 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\os\hal\platforms\STM32\SPIv1;..\..\..\os\hal\platforms\STM32\TIMv1;..\..\..\os\hal\platforms\STM32\USARTv1;..\..\..\os\hal\platforms\STM32F4xx;..\..\..\os\various;..\..\..\os\various\devices_lib\accel;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s + + + nvic.c + 1 + ..\..\..\os\ports\common\ARMCMx\nvic.c + + + nvic.h + 5 + ..\..\..\os\ports\common\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\TIMv1\pwm_lld.c + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\TIMv1\pwm_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\USARTv1\serial_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\SPIv1\spi_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + stm32f4xx.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/main.c b/main.c new file mode 100644 index 0000000..000ce57 --- /dev/null +++ b/main.c @@ -0,0 +1,349 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#include "various/chprintf.h" +#include "various/shell.h" //otherwise will comcflict with elua +#include "lis302dl.h" + +#include "usbcfg.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +BaseSequentialStream *eLuaSDriver; +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(2048) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {THD_STATE_NAMES}; + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state], (uint32_t)tp->p_time); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Accelerometer related. */ +/*===========================================================================*/ + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 1 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static const PWMConfig pwmcfg = { + 100000, /* 100kHz PWM clock frequency. */ + 128, /* PWM period is 128 cycles. */ + NULL, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + /* HW dependent part.*/ + 0, + 0 +}; + +/* + * SPI1 configuration structure. + * Speed 5.25MHz, CPHA=1, CPOL=1, 8bits frames, MSb transmitted first. + * The slave select line is the pin GPIOE_CS_SPI on the port GPIOE. + */ +static const SPIConfig spi1cfg = { + NULL, + /* HW dependent part.*/ + GPIOE, + GPIOE_CS_SPI, + SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_CPOL | SPI_CR1_CPHA +}; + +/* + * SPI2 configuration structure. + * Speed 21MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first. + * The slave select line is the pin 12 on the port GPIOA. + */ +static const SPIConfig spi2cfg = { + NULL, + /* HW dependent part.*/ + GPIOB, + 12, + 0 +}; + +/* + * This is a periodic thread that reads accelerometer and outputs + * result to SPI2 and PWM. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + static int8_t xbuf[4], ybuf[4]; /* Last accelerometer data.*/ + systime_t time; /* Next deadline.*/ + + (void)arg; + chRegSetThreadName("reader"); + + /* LIS302DL initialization.*/ + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG1, 0x43); + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG2, 0x00); + lis302dlWriteRegister(&SPID1, LIS302DL_CTRL_REG3, 0x00); + + /* Reader thread loop.*/ + time = chTimeNow(); + while (TRUE) { + int32_t x, y; + unsigned i; + + /* Keeping an history of the latest four accelerometer readings.*/ + for (i = 3; i > 0; i--) { + xbuf[i] = xbuf[i - 1]; + ybuf[i] = ybuf[i - 1]; + } + + /* Reading MEMS accelerometer X and Y registers.*/ + xbuf[0] = (int8_t)lis302dlReadRegister(&SPID1, LIS302DL_OUTX); + ybuf[0] = (int8_t)lis302dlReadRegister(&SPID1, LIS302DL_OUTY); + + /* Transmitting accelerometer the data over SPI2.*/ + spiSelect(&SPID2); + spiSend(&SPID2, 4, xbuf); + spiSend(&SPID2, 4, ybuf); + spiUnselect(&SPID2); + + /* Calculating average of the latest four accelerometer readings.*/ + x = ((int32_t)xbuf[0] + (int32_t)xbuf[1] + + (int32_t)xbuf[2] + (int32_t)xbuf[3]) / 4; + y = ((int32_t)ybuf[0] + (int32_t)ybuf[1] + + (int32_t)ybuf[2] + (int32_t)ybuf[3]) / 4; + + /* Reprogramming the four PWM channels using the accelerometer data.*/ + if (y < 0) { + pwmEnableChannel(&PWMD4, 0, (pwmcnt_t)-y); + pwmEnableChannel(&PWMD4, 2, (pwmcnt_t)0); + } + else { + pwmEnableChannel(&PWMD4, 2, (pwmcnt_t)y); + pwmEnableChannel(&PWMD4, 0, (pwmcnt_t)0); + } + if (x < 0) { + pwmEnableChannel(&PWMD4, 1, (pwmcnt_t)-x); + pwmEnableChannel(&PWMD4, 3, (pwmcnt_t)0); + } + else { + pwmEnableChannel(&PWMD4, 3, (pwmcnt_t)x); + pwmEnableChannel(&PWMD4, 1, (pwmcnt_t)0); + } + + /* Waiting until the next 250 milliseconds time interval.*/ + chThdSleepUntil(time += MS2ST(100)); + } +} + +static WORKING_AREA(waUSB_THREAD, 512); +static msg_t USB_THREAD(void *arg) { + (void)arg; + Thread *shelltp = NULL; + + /* + * Normal main() thread activity, in this demo it just performs + * a shell respawn upon its termination. + */ + while (TRUE) { + if (!shelltp) { + if (SDU1.config->usbp->state == USB_ACTIVE) { + /* Spawns a new shell.*/ + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + } + } + else { + /* If the previous shell exited.*/ + if (chThdTerminated(shelltp)) { + /* Recovers memory of the previous shell.*/ + chThdRelease(shelltp); + shelltp = NULL; + } + } + chThdSleepMilliseconds(500); + } + +} +/*===========================================================================*/ +/* Initialization and main thread. */ +/*===========================================================================*/ + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART2. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * Initializes the SPI driver 1 in order to access the MEMS. The signals + * are already initialized in the board file. + */ + spiStart(&SPID1, &spi1cfg); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ + spiStart(&SPID2, &spi2cfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOD, GPIOD_LED4, PAL_MODE_ALTERNATE(2)); /* Green. */ + palSetPadMode(GPIOD, GPIOD_LED3, PAL_MODE_ALTERNATE(2)); /* Orange. */ + palSetPadMode(GPIOD, GPIOD_LED5, PAL_MODE_ALTERNATE(2)); /* Red. */ + palSetPadMode(GPIOD, GPIOD_LED6, PAL_MODE_ALTERNATE(2)); /* Blue. */ + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO + 10, Thread1, NULL); + + #if !defined(CHIBILUA_USBSERIAL) && !defined(CHIBILUA_SERIAL) + #error "please chose CHIBILUA_USBSERIAL or CHIBILUA_SERIAL in halconf.h" + #elif defined(CHIBILUA_USBSERIAL) && !defined(CHIBILUA_SERIAL) + eLuaSDriver=(BaseSequentialStream *)&SDU1; //elua shell on USB serial + #elif defined(CHIBILUA_SERIAL) && !defined(CHIBILUA_USBSERIAL) + eLuaSDriver=(BaseSequentialStream *)&SD2; //elua shell on uart serial + chThdCreateStatic(waUSB_THREAD, sizeof(waUSB_THREAD), NORMALPRIO, USB_THREAD, NULL); + #else + #error "can't use CHIBILUA_USBSERIAL and CHIBILUA_SERIAL in same time" + #endif + + main_lua();//while(1) !!! but could exit + + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/mcuconf.h b/mcuconf.h new file mode 100644 index 0000000..f753b0a --- /dev/null +++ b/mcuconf.h @@ -0,0 +1,288 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..527e690 --- /dev/null +++ b/readme.md @@ -0,0 +1,31 @@ +example how to run eLua with chibios +==================================== + +Example how to run eLua with chibios on STM32F4_DISCOVERY. + +eLua use its own memory management so, my solution is split memory, one part for chibios and second for eLua (refer to STM32F407xG.ld) +This demo is based on original ChibiOS/demos/ARMCM4-STM32F407-DISCOVERY-MEMS + + +Quick start +---------------- +mkdir -p ~/src/elua_chibios/ +cd -p ~/src/elua_chibios/ +git clone https://github.com/ChibiOS/ChibiOS.git +git clone https://github.com/linvinus/chibios_with_elua.git +cd ~/src/elua_chibios/chibios_with_elua/ext/ +git clone https://github.com/elua/elua.git +cd ~/src/elua_chibios/chibios_with_elua +make + +upload to STM32F4_DISCOVERY +by default elua avaylable on USB serial (ttyACM0 in linux). +you may switch to serial driver in halconf.h + +License +------- +Note, ChibiOS licensed under different licenses (Pure GPL3,GPL3 with Exception,Commercial). +While eLua licensed under MIT. +For more info refer to original sources. +http://www.chibios.org/dokuwiki/doku.php?id=chibios:license +http://www.eluaproject.net/overview/license diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..940e073 --- /dev/null +++ b/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use PWM and SPI drivers using synchronous APIs. The PWM +driver the four board LEDs with the data read from the LIS320DL accelerometer. +The data is also transmitted on the SPI2 port. +A simple command shell is activated on virtual serial port SD2 via USB-CDC +driver (use micro-USB plug on STM32F4-Discovery board). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/rules.mk b/rules.mk new file mode 100644 index 0000000..52efda1 --- /dev/null +++ b/rules.mk @@ -0,0 +1,257 @@ +# ARM Cortex-Mx common makefile scripts and rules. + +############################################################################## +# Processing options coming from the upper Makefile. +# + +# Compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) + +# Garbage collection +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections -fno-common + LDOPT := ,--gc-sections +else + LDOPT := +endif + +# Linker extra options +ifneq ($(USE_LDOPT),) + LDOPT := $(LDOPT),$(USE_LDOPT) +endif + +# Link time optimizations +ifeq ($(USE_LTO),yes) + OPT += -flto +endif + +# FPU-related options +ifeq ($(USE_FPU),) + USE_FPU = no +endif +ifneq ($(USE_FPU),no) + OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant + DDEFS += -DCORTEX_USE_FPU=TRUE + DADEFS += -DCORTEX_USE_FPU=TRUE +else + DDEFS += -DCORTEX_USE_FPU=FALSE + DADEFS += -DCORTEX_USE_FPU=FALSE +endif + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)) ) + + #$(dir $(ELUA_ALL_CSRC)) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +#ELUAOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ELUA_CSRC:.c=_elua.o))) +OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(ELUA_ALL_OBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT) + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +ASFLAGS += -MD -MP -MF .dep/$(@F).d +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo + @$(SZ) $< + @echo + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo + @echo Done + + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/usbcfg.c b/usbcfg.c new file mode 100644 index 0000000..24955b8 --- /dev/null +++ b/usbcfg.c @@ -0,0 +1,314 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromIsr(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromIsr(); + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + NULL +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/usbcfg.h b/usbcfg.h new file mode 100644 index 0000000..6301573 --- /dev/null +++ b/usbcfg.h @@ -0,0 +1,25 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _USBCFG_H_ +#define _USBCFG_H_ + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; + +#endif /* _USBCFG_H_ */ + +/** @} */