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we need TLE8888 driver #714

This commit is contained in:
rusefi 2019-04-06 12:26:37 -04:00
parent dd09ea7d90
commit 131533cc13
2 changed files with 4 additions and 8 deletions
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6
firmware/config/engines/custom_engine.cpp
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@ -319,7 +319,6 @@ void setTle8888TestConfiguration(DECLARE_ENGINE_PARAMETER_SIGNATURE) {
engineConfiguration->crankingInjectionMode = IM_SEQUENTIAL; engineConfiguration->crankingInjectionMode = IM_SEQUENTIAL;
engineConfiguration->tle8888_cs = GPIOD_5; engineConfiguration->tle8888_cs = GPIOD_5;
// engineConfiguration->tle8888_csPinMode = OM_OPENDRAIN;
engineConfiguration->directSelfStimulation = true; engineConfiguration->directSelfStimulation = true;
boardConfiguration->ignitionPins[0] = GPIOG_3; boardConfiguration->ignitionPins[0] = GPIOG_3;
@ -336,11 +335,6 @@ void setTle8888TestConfiguration(DECLARE_ENGINE_PARAMETER_SIGNATURE) {
// PB3 is nicely both SWO and SPI1 SCK so logic analyzer could be used on SWO header // PB3 is nicely both SWO and SPI1 SCK so logic analyzer could be used on SWO header
boardConfiguration->is_enabled_spi_1 = true; boardConfiguration->is_enabled_spi_1 = true;
engineConfiguration->debugMode = DBG_TLE8888; engineConfiguration->debugMode = DBG_TLE8888;
// engineConfiguration->spi1MosiMode = PO_OPENDRAIN;
// engineConfiguration->spi1MisoMode = PO_PULLUP;
// engineConfiguration->spi1SckMode = PO_OPENDRAIN;
} }
#endif /* CONFIG_ENGINES_CUSTOM_ENGINE_CPP_ */ #endif /* CONFIG_ENGINES_CUSTOM_ENGINE_CPP_ */

6
firmware/hw_layer/drivers/gpio/tle8888.c
View File

@ -3,6 +3,9 @@
* *
* TLE8888 Engine Machine System IC driver * TLE8888 Engine Machine System IC driver
* *
* This has worked on a bench - see https://youtu.be/yjs5dh_NKo4
* All SPI and CS pin in OM_DEFAULT mode
*
* @date Mar 25, 2019 * @date Mar 25, 2019
* @author Andrey Belomutskiy, (c) 2012-2019 * @author Andrey Belomutskiy, (c) 2012-2019
* *
@ -299,8 +302,7 @@ static struct tle8888_config tle8888_cfg = {
SPI_CR1_LSBFIRST | //LSB first SPI_CR1_LSBFIRST | //LSB first
((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | // div = 16 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) | // div = 16
SPI_CR1_MSTR | SPI_CR1_MSTR |
// SPI_CR1_CPOL | // = 0 CHECK! SPI_CR1_CPHA
SPI_CR1_CPHA | // = 1 CHECK!
0, 0,
.cr2 = 0/* not for F4? SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0*/ .cr2 = 0/* not for F4? SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0*/
}, },