auto detect HSE clock speed (#2952)
* detect hse * implementation * these boards don't need to set their own HSECLK * assertions * name * tweaks * how did this compile? * s * biiiig comment * this script doesn't need to set 25mhz any more * ....or PLLM Co-authored-by: Matthew Kennedy <makenne@microsoft.com>
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Matthew Kennedy
GitHub
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@ -5,7 +5,7 @@ rem TODO: somehow this -DDUMMY is helping us to not mess up the parameters, why?
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rem https://github.com/rusefi/rusefi/issues/684
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rem this board has only 512K flash so using custom FLASH_ADDR
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rem You probably want "flash0 : org = 0x08000000, len = 450K" in the .ld file
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set EXTRA_PARAMS=-DDUMMY -DEFI_COMMUNICATION_PIN=GPIOB_9 -DSTM32_HSECLK=25000000U -DSTM32_PLLM_VALUE=25 -DSTM32_RTCPRE_VALUE=25 -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS^
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set EXTRA_PARAMS=-DDUMMY -DEFI_COMMUNICATION_PIN=GPIOB_9 -DSTM32_RTCPRE_VALUE=25 -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS^
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-DEFI_INTERNAL_FLASH=FALSE ^
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-DHAL_USE_RTC=FALSE ^
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-DBOARD_OTG_NOVBUSSENS ^
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@ -57,10 +57,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -57,10 +57,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -57,10 +57,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -57,10 +57,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -57,10 +57,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -41,10 +41,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -28,10 +28,6 @@
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#define STM32_LSEDRV (3U << 3U)
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 25000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -11,10 +11,6 @@
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#include "../../../hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h"
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/* clocks adjust for 25 MHz ocs */
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#undef STM32_PLLM_VALUE
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#define STM32_PLLM_VALUE 25
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//#undef STM32_LSE_ENABLED
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//#define STM32_LSE_ENABLED FALSE
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@ -323,3 +323,15 @@
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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// We auto detect the value of HSE, so set the default PLLM value to the maximum,
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// so we don't accidentially overclock to processor before we know how fast HSE is
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#define STM32_PLLM_VALUE 25
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// This also means we have to pretend (for now) we have a 25MHz HSE fitted
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#define STM32_HSECLK 25000000
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// After boot, we will detect the real frequency, and adjust the PLL M value to suit
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#define ENABLE_AUTO_DETECT_HSE
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@ -0,0 +1,130 @@
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/**
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* @file osc_detector.cpp
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* @brief This logic automatically detects the speed of the
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* oscillator or crystal connected to HSE.
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* @date 12 July 2021
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*
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* It works by first using the reasonably-precise HSI oscillator (16MHz) to measure LSI (nominally 32khz, but wide tolerance).
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* Then, it switches the system clock source to HSE, and repeats the same measurement. The inaccurate LSI will not drift
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* significantly in the short period of time between these two measurements, so use it as a transfer standard to compare the speed
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* of HSI and HSE. The ratio between the measured speed of LSI when running on HSE vs. HSI will give the ratio of speeds of HSE
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* and HSI themselves. Since we know the value of HSI (16mhz), we can compute the speed of HSE.
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*
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* Lastly, the PLL is reconfigured to use the correct input divider such that the input frequency is 1MHz
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* (PLLM is set to N for an N-MHz HSE crystal).
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*/
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#include "hal.h"
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#include "efilib.h"
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#ifdef ENABLE_AUTO_DETECT_HSE
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static void useHsi() {
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// clear SW to use HSI
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RCC->CFGR &= ~RCC_CFGR_SW;
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}
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static void useHse() {
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// Switch to HSE clock
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RCC->CFGR &= ~RCC_CFGR_SW;
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RCC->CFGR |= RCC_CFGR_SW_HSE;
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}
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static void usePll() {
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RCC->CFGR &= ~RCC_CFGR_SW;
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2));
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}
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static uint32_t getOneCapture() {
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// wait for input capture
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while ((TIM5->SR & TIM_SR_CC4IF) == 0);
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// Return captured count
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return TIM5->CCR4;
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}
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static uint32_t getAverageLsiCounts() {
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// Burn one count
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getOneCapture();
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uint32_t lastCapture = getOneCapture();
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uint32_t sum = 0;
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for (size_t i = 0; i < 20; i++)
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{
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auto capture = getOneCapture();
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sum += (capture - lastCapture);
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lastCapture = capture;
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}
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return sum;
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}
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// This only works if you're using the PLL as the configured clock source!
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static_assert(STM32_SW == RCC_CFGR_SW_PLL);
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// These clocks must all be enabled for this to work
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static_assert(STM32_HSI_ENABLED);
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static_assert(STM32_LSI_ENABLED);
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static_assert(STM32_HSE_ENABLED);
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static void reprogramPll(uint8_t pllM) {
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// Switch back to HSI to configure PLL
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useHsi();
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// Stop the PLL
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RCC->CR &= ~RCC_CR_PLLON;
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// Mask out the old PLLM val
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RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM_Msk;
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// Stick in the new PLLM value
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RCC->PLLCFGR |= (pllM << RCC_PLLCFGR_PLLM_Pos) & RCC_PLLCFGR_PLLM_Msk;
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// Reenable PLL, wait for lock
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY));
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// Switch clock source back to PLL
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usePll();
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}
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// __late_init runs after bss/zero initialziation, but before static constructors and main
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extern "C" void __late_init() {
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// Turn on timer 5
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
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// Remap to connect LSI to input capture channel 4
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TIM5->OR = TIM_OR_TI4_RMP_0;
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// Enable capture on channel 4
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TIM5->CCMR2 = TIM_CCMR2_CC4S_0;
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TIM5->CCER = TIM_CCER_CC4E;
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// Start TIM5
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TIM5->CR1 |= TIM_CR1_CEN;
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// Use HSI
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useHsi();
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// Measure LSI against HSI
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auto hsiCounts = getAverageLsiCounts();
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useHse();
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// Measure LSI against HSE
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auto hseCounts = getAverageLsiCounts();
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// Turn off timer 5 now that we're done with it
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
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// The external clocks's frequency is the ratio of the measured LSI speed, times HSI's speed (16MHz)
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float hseFrequencyMhz = 16.0f * hseCounts / hsiCounts;
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uint8_t pllMValue = efiRound(hseFrequencyMhz, 1);
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reprogramPll(pllMValue);
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}
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#endif // defined ENABLE_AUTO_DETECT_HSE
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@ -7,6 +7,7 @@ HW_LAYER_EMS_CPP += \
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$(PROJECT_DIR)/hw_layer/ports/stm32/stm32_common.cpp \
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$(PROJECT_DIR)/hw_layer/ports/stm32/backup_ram.cpp \
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$(PROJECT_DIR)/hw_layer/ports/stm32/microsecond_timer_stm32.cpp \
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$(PROJECT_DIR)/hw_layer/ports/stm32/osc_detector.cpp \
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RUSEFIASM = $(PROJECT_DIR)/hw_layer/ports/stm32/rusEfiStartup.S
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@ -56,10 +56,6 @@
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#define STM32_LSECLK 32768U
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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@ -53,9 +53,6 @@
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#ifndef STM32_PLLM_VALUE
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#define STM32_PLLM_VALUE 8
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#endif
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 7
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@ -58,10 +58,6 @@
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#define STM32_LSEDRV (3U << 3U)
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U
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#endif
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// Nucleo boards use MCO signal from St-Link and NOT oscillator - these need STM32_HSE_BYPASS
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// if you do not have Sl-Link and MCO on your board, you need EFI_USE_OSC
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 432
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 9
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