rusefi
/
custom-board-bundle-sample-fork-of-rusefi
mirror of https://github.com/rusefi/custom-board-bundle-sample-fork-of-rusefi.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Turned on courtyards layers.

This commit is contained in:
jharvey 2020-05-20 19:22:27 -04:00
parent 125701f514
commit 20e7d7baad
2 changed files with 637 additions and 312 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

603
hardware/frankenso/frankenso.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

346
hardware/frankenso/frankenso.pro
View File

@ -1,4 +1,4 @@
update=3/22/2020 10:13:11 AM
update=5/20/2020 7:18:35 PM
version=1
last_client=kicad
[cvpcb]
@ -8,25 +8,6 @@ NetIExt=net
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
LastNetListRead=frankenso.net
PadDrill=0
PadDrillOvalY=0
PadSizeH=0.70104
PadSizeV=1.6002
PcbTextSizeV=1.016
PcbTextSizeH=1.016
PcbTextThickness=0.127
ModuleTextSizeV=0.508
ModuleTextSizeH=0.508
ModuleTextSizeThickness=0.127
SolderMaskClearance=0.2
SolderMaskMinWidth=0
DrawSegmentWidth=0.127
BoardOutlineThickness=0.127
ModuleOutlineThickness=0.254
[schematic_editor]
version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
@ -40,3 +21,328 @@ LabSize=60
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
LastNetListRead=frankenso.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0
MinViaDrill=0.3302
MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.1524
TrackWidth3=0.2159
TrackWidth4=0.3048
TrackWidth5=1.0668
TrackWidth6=1.651
TrackWidth7=1.6764
TrackWidth8=2.7178
ViaDiameter1=0.6858
ViaDrill1=0.3302
ViaDiameter2=0.6858
ViaDrill2=0.3302
ViaDiameter3=0.78994
ViaDrill3=0.43434
ViaDiameter4=1.54178
ViaDrill4=1.18618
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.254
SilkTextSizeV=0.508
SilkTextSizeH=0.508
SilkTextSizeThickness=0.127
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.127
CopperTextSizeV=1.016
CopperTextSizeH=1.016
CopperTextThickness=0.127
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.127
CourtyardLineWidth=0.05
OthersLineWidth=0.254
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=PWR
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=GND
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=1A external
Clearance=0.2159
TrackWidth=0.3048
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=2.5A external
Clearance=0.2159
TrackWidth=1.0668
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=3.5A external
Clearance=0.2159
TrackWidth=1.651
ViaDiameter=1.0922
ViaDrill=0.6858
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=3.5A external high voltage
Clearance=1.016
TrackWidth=1.6764
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/5]
Name=5A external
Clearance=0.2159
TrackWidth=2.7178
ViaDiameter=1.54178
ViaDrill=1.18618
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/6]
Name=Supply_200V
Clearance=0.3048
TrackWidth=1.0668
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/7]
Name=min2_extern_.188A
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/8]
Name=min_extern_.241A
Clearance=0.2159
TrackWidth=0.2159
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25