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custom-board-bundle-sample-fork-of-rusefi
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rusEfi 2015-07-27 13:03:47 -04:00
parent 2d7a049089
commit 7e5cfe1d8b
4 changed files with 1277 additions and 0 deletions
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(kicad_pcb (version 4) (host pcbnew "(2015-07-02 BZR 5871, Git 766da1e)-product")
(general
(links 14)
(no_connects 0)
(area 143.175999 97.2365 170.716334 130.769)
(thickness 1.6)
(drawings 6)
(tracks 212)
(zones 0)
(modules 8)
(nets 15)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(user_trace_width 0.3125)
(user_trace_width 0.375)
(user_trace_width 0.4375)
(user_trace_width 0.5625)
(user_trace_width 0.625)
(user_trace_width 0.6875)
(user_trace_width 0.75)
(user_trace_width 0.8125)
(user_trace_width 0.875)
(user_trace_width 0.9375)
(user_trace_width 1)
(user_trace_width 1.6)
(trace_clearance 0.2)
(zone_clearance 0.254)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.2)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(user_via 0.4 0.2)
(user_via 0.6 0.4)
(user_via 0.8 0.6)
(user_via 1 0.8)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5)
(pad_drill 0.6)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x010f0_80000001)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk true)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory Gerbers/))
)
(net 0 "")
(net 1 "Net-(D1-Pad2)")
(net 2 +12V)
(net 3 "Net-(P1-Pad1)")
(net 4 "Net-(P1-Pad2)")
(net 5 GND)
(net 6 "Net-(P1-Pad7)")
(net 7 "Net-(Q1-Pad1)")
(net 8 "Net-(Q1-Pad2)")
(net 9 "Net-(Q1-Pad3)")
(net 10 "Net-(Q1-Pad4)")
(net 11 "Net-(P1-Pad4)")
(net 12 "Net-(P1-Pad5)")
(net 13 "Net-(P1-Pad8)")
(net 14 +5V)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +12V)
(add_net +5V)
(add_net GND)
(add_net "Net-(D1-Pad2)")
(add_net "Net-(P1-Pad1)")
(add_net "Net-(P1-Pad2)")
(add_net "Net-(P1-Pad4)")
(add_net "Net-(P1-Pad5)")
(add_net "Net-(P1-Pad7)")
(add_net "Net-(P1-Pad8)")
(add_net "Net-(Q1-Pad1)")
(add_net "Net-(Q1-Pad2)")
(add_net "Net-(Q1-Pad3)")
(add_net "Net-(Q1-Pad4)")
)
(module VN750PS_E_Vertical:VN750PS-E (layer F.Cu) (tedit 55A9404C) (tstamp 55A7DC0D)
(at 160.655 109.6645 270)
(path /55A7C4D6)
(fp_text reference Q1 (at -0.1905 -0.381 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VN750PS_E (at -1.778 -3.683 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -1.45542 -2.0066 270) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.0625)))
)
(fp_line (start -1.92532 -2.58064) (end 1.72468 -2.58064) (layer F.SilkS) (width 0.15))
(fp_line (start 1.72974 -2.5908) (end 1.72974 2.4092) (layer F.SilkS) (width 0.15))
(fp_line (start -1.92024 2.413) (end 1.72976 2.413) (layer F.SilkS) (width 0.15))
(fp_line (start -1.92024 -2.58826) (end -1.92024 2.41174) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.69772 -1.9491 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(Q1-Pad1)"))
(pad 2 smd rect (at -2.69772 -0.6791 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(Q1-Pad2)"))
(pad 3 smd rect (at -2.69772 0.5909 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(Q1-Pad3)"))
(pad 4 smd rect (at -2.69772 1.8609 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 10 "Net-(Q1-Pad4)"))
(pad 5 smd rect (at 2.50228 1.8609 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 2 +12V))
(pad 6 smd rect (at 2.50228 0.5909 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 1 "Net-(D1-Pad2)"))
(pad 7 smd rect (at 2.50228 -0.6791 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 1 "Net-(D1-Pad2)"))
(pad 8 smd rect (at 2.50228 -1.9491 180) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask)
(net 2 +12V))
)
(module VN750PS_E_Vertical:US1GHE3 (layer B.Cu) (tedit 55A7DD5A) (tstamp 55A7DD9E)
(at 160.8455 114.808)
(path /55A7C862)
(fp_text reference D1 (at 0.28956 -1.95072) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value D (at 0.1524 2.37744) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -3.03276 0.87376) (end -3.03276 -0.87376) (layer B.SilkS) (width 0.15))
(pad 2 smd rect (at 1.778 -0.01868) (size 1.6 1.7) (layers B.Cu B.Paste B.Mask)
(net 1 "Net-(D1-Pad2)"))
(pad 1 smd rect (at -1.69662 -0.01868) (size 1.6 1.7) (layers B.Cu B.Paste B.Mask)
(net 2 +12V))
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 55A9402F) (tstamp 55A7E046)
(at 162.433 103.378 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /55A7C95A)
(attr smd)
(fp_text reference R1 (at -2.6035 -0.6985 360) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 130 (at -4.953 -0.0635 270) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 5 GND))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(Q1-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 55A9402D) (tstamp 55A7E04C)
(at 160.782 103.378 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /55A7C9E2)
(attr smd)
(fp_text reference R2 (at -2.6035 0.1905 360) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at -4.8895 0.0635 270) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(P1-Pad5)"))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(Q1-Pad2)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Angled_1x08 (layer F.Cu) (tedit 55A80529) (tstamp 55A7E328)
(at 154.051 120.0785 180)
(descr "Through hole pin header")
(tags "pin header")
(path /55A7E2A2)
(fp_text reference P1 (at 0 -5.1 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_01X08 (at 0.254 -3.683 180) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -1.75) (end -1.5 19.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.65 -1.75) (end 10.65 19.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 -1.75) (end 10.65 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 19.55) (end 10.65 19.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -1.55) (end -1.3 0) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.55) (end -1.3 -1.55) (layer F.SilkS) (width 0.15))
(fp_line (start 4.191 -0.127) (end 10.033 -0.127) (layer F.SilkS) (width 0.15))
(fp_line (start 10.033 -0.127) (end 10.033 0.127) (layer F.SilkS) (width 0.15))
(fp_line (start 10.033 0.127) (end 4.191 0.127) (layer F.SilkS) (width 0.15))
(fp_line (start 4.191 0.127) (end 4.191 0) (layer F.SilkS) (width 0.15))
(fp_line (start 4.191 0) (end 10.033 0) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 17.526) (end 1.143 17.526) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 18.034) (end 1.143 18.034) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 -0.254) (end 1.143 -0.254) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 0.254) (end 1.143 0.254) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 2.286) (end 1.143 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 2.794) (end 1.143 2.794) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 4.826) (end 1.143 4.826) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 5.334) (end 1.143 5.334) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 15.494) (end 1.143 15.494) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 14.986) (end 1.143 14.986) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 12.446) (end 1.143 12.446) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 10.414) (end 1.143 10.414) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 9.906) (end 1.143 9.906) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 7.874) (end 1.143 7.874) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 7.366) (end 1.143 7.366) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 13.97) (end 4.064 13.97) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 13.97) (end 1.524 16.51) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 16.51) (end 4.064 16.51) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 14.986) (end 10.16 14.986) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 14.986) (end 10.16 15.494) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 15.494) (end 4.064 15.494) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 16.51) (end 4.064 13.97) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 19.05) (end 4.064 16.51) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 18.034) (end 4.064 18.034) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 17.526) (end 10.16 18.034) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 17.526) (end 10.16 17.526) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 16.51) (end 1.524 19.05) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 16.51) (end 4.064 16.51) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 19.05) (end 4.064 19.05) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 -1.27) (end 4.064 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 1.27) (end 4.064 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 1.27) (end 1.524 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 3.81) (end 4.064 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 2.286) (end 10.16 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 2.286) (end 10.16 2.794) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 2.794) (end 4.064 2.794) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 3.81) (end 4.064 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 1.27) (end 4.064 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 0.254) (end 4.064 0.254) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 -0.254) (end 10.16 0.254) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 -0.254) (end 10.16 -0.254) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 1.27) (end 4.064 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 -1.27) (end 1.524 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 8.89) (end 4.064 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 8.89) (end 1.524 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 11.43) (end 4.064 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 9.906) (end 10.16 9.906) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 9.906) (end 10.16 10.414) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 10.414) (end 4.064 10.414) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 11.43) (end 4.064 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 13.97) (end 4.064 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 12.954) (end 4.064 12.954) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 12.446) (end 10.16 12.954) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 12.446) (end 10.16 12.446) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 13.97) (end 4.064 13.97) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 11.43) (end 1.524 13.97) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 11.43) (end 4.064 11.43) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 6.35) (end 4.064 6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 6.35) (end 1.524 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 8.89) (end 4.064 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 7.366) (end 10.16 7.366) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 7.366) (end 10.16 7.874) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 7.874) (end 4.064 7.874) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 8.89) (end 4.064 6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 6.35) (end 4.064 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 5.334) (end 4.064 5.334) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 4.826) (end 10.16 5.334) (layer F.SilkS) (width 0.15))
(fp_line (start 4.064 4.826) (end 10.16 4.826) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 6.35) (end 4.064 6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 3.81) (end 1.524 6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 1.524 3.81) (end 4.064 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 3 "Net-(P1-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 4 "Net-(P1-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 14 +5V))
(pad 4 thru_hole oval (at 0 7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 11 "Net-(P1-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 12 "Net-(P1-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 5 GND))
(pad 7 thru_hole oval (at 0 15.24 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 6 "Net-(P1-Pad7)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
(net 13 "Net-(P1-Pad8)"))
(model Pin_Headers.3dshapes/Pin_Header_Angled_1x08.wrl
(at (xyz 0 -0.35 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 55A94039) (tstamp 55A7F5AC)
(at 156.4005 103.378 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /55A7CA15)
(attr smd)
(fp_text reference R3 (at 2.6035 1.778 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 5.0165 -0.1905 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(P1-Pad4)"))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(Q1-Pad3)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 55A94021) (tstamp 55A7F5B2)
(at 158.0515 103.378 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /55A7CA70)
(attr smd)
(fp_text reference R4 (at 2.6035 -2.2225 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 5.0165 0.254 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 14 +5V))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(Q1-Pad3)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module VN750PS_E_Vertical:Pin_Header_Straight_25x02 (layer F.Cu) (tedit 55A931A2) (tstamp 55A9325D)
(at 157.9245 118.8085 90)
(descr "Through hole pin header")
(tags "pin header")
(path /55A7CFB7)
(fp_text reference P2 (at -10.9855 5.334 90) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_01X02 (at -8.382 7.6835 90) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 90) (size 3.2 3.2) (drill 1.6) (layers *.Cu *.Mask F.SilkS)
(net 2 +12V))
(pad 2 thru_hole oval (at 0 6.35 90) (size 3.2 3.2) (drill 1.6) (layers *.Cu *.Mask F.SilkS)
(net 1 "Net-(D1-Pad2)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(gr_text OUT (at 165.2905 114.935 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text 12V (at 156.718 114.935 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_line (start 167 122) (end 167 100) (angle 90) (layer Edge.Cuts) (width 0.2) (tstamp 55A7DF94))
(gr_line (start 150 122) (end 167 122) (angle 90) (layer Edge.Cuts) (width 0.2) (tstamp 55A7DF71))
(gr_line (start 150 100) (end 167 100) (angle 90) (layer Edge.Cuts) (width 0.2))
(gr_line (start 150 122) (end 150 100) (angle 90) (layer Edge.Cuts) (width 0.2))
(segment (start 162.6235 116.1415) (end 162.2425 116.1415) (width 0.25) (layer F.Cu) (net 1))
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(segment (start 162.2425 116.1415) (end 161.798 116.586) (width 0.25) (layer F.Cu) (net 1) (tstamp 55A94DDB))
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62
hardware/HighSideSwitch/VN750PS_E.pro Normal file
View File

@ -0,0 +1,62 @@
update=7/17/2015 12:48:22 PM
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=vn750ps_e
LibName31=C:/rusefi/SpillyHardware/VN5E050AJ_E_Vertical/VN5E050AJ_E
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
PadDrill=0.6
PadDrillOvalY=0.6
PadSizeH=1.5
PadSizeV=1.5
PcbTextSizeV=1.5
PcbTextSizeH=1.5
PcbTextThickness=0.3
ModuleTextSizeV=1
ModuleTextSizeH=1
ModuleTextSizeThickness=0.15
SolderMaskClearance=0
SolderMaskMinWidth=0
DrawSegmentWidth=0.2
BoardOutlineThickness=0.2
ModuleOutlineThickness=0.15

228
hardware/HighSideSwitch/VN750PS_E.sch Normal file
View File

@ -0,0 +1,228 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:vn750ps_e
LIBS:VN5E050AJ_E
LIBS:VN750PS_E-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L VN750PS_E Q1
U 1 1 55A7C4D6
P 3750 4400
F 0 "Q1" H 5600 4850 60 0000 C CNN
F 1 "VN750PS_E" H 5600 6050 60 0000 C CNN
F 2 "VN750PS_E_Vertical:VN750PS-E" H 5600 4850 60 0001 C CNN
F 3 "" H 5600 4850 60 0000 C CNN
1 3750 4400
1 0 0 -1
$EndComp
$Comp
L D D1
U 1 1 55A7C862
P 6600 3300
F 0 "D1" H 6600 3400 50 0000 C CNN
F 1 "D" H 6600 3200 50 0000 C CNN
F 2 "VN750PS_E_Vertical:US1GHE3" H 6600 3300 60 0001 C CNN
F 3 "" H 6600 3300 60 0000 C CNN
1 6600 3300
0 1 1 0
$EndComp
$Comp
L R R1
U 1 1 55A7C95A
P 4600 3050
F 0 "R1" V 4680 3050 50 0000 C CNN
F 1 "130" V 4600 3050 50 0000 C CNN
F 2 "Resistors_SMD:R_0603_HandSoldering" V 4530 3050 30 0001 C CNN
F 3 "" H 4600 3050 30 0000 C CNN
1 4600 3050
0 -1 -1 0
$EndComp
$Comp
L R R2
U 1 1 55A7C9E2
P 4600 3300
F 0 "R2" V 4680 3300 50 0000 C CNN
F 1 "10k" V 4600 3300 50 0000 C CNN
F 2 "Resistors_SMD:R_0603_HandSoldering" V 4530 3300 30 0001 C CNN
F 3 "" H 4600 3300 30 0000 C CNN
1 4600 3300
0 -1 -1 0
$EndComp
$Comp
L R R3
U 1 1 55A7CA15
P 4600 3550
F 0 "R3" V 4680 3550 50 0000 C CNN
F 1 "10k" V 4600 3550 50 0000 C CNN
F 2 "Resistors_SMD:R_0603_HandSoldering" V 4530 3550 30 0001 C CNN
F 3 "" H 4600 3550 30 0000 C CNN
1 4600 3550
0 -1 -1 0
$EndComp
$Comp
L R R4
U 1 1 55A7CA70
P 4600 3750
F 0 "R4" V 4680 3750 50 0000 C CNN
F 1 "10k" V 4600 3750 50 0000 C CNN
F 2 "Resistors_SMD:R_0603_HandSoldering" V 4530 3750 30 0001 C CNN
F 3 "" H 4600 3750 30 0000 C CNN
1 4600 3750
0 -1 -1 0
$EndComp
$Comp
L +12V #PWR01
U 1 1 55A7CAF7
P 6600 2700
F 0 "#PWR01" H 6600 2550 50 0001 C CNN
F 1 "+12V" H 6600 2840 50 0000 C CNN
F 2 "" H 6600 2700 60 0000 C CNN
F 3 "" H 6600 2700 60 0000 C CNN
1 6600 2700
1 0 0 -1
$EndComp
$Comp
L GND #PWR02
U 1 1 55A7CB37
P 4150 3050
F 0 "#PWR02" H 4150 2800 50 0001 C CNN
F 1 "GND" H 4150 2900 50 0000 C CNN
F 2 "" H 4150 3050 60 0000 C CNN
F 3 "" H 4150 3050 60 0000 C CNN
1 4150 3050
1 0 0 -1
$EndComp
$Comp
L CONN_01X02 P2
U 1 1 55A7CFB7
P 7200 3200
F 0 "P2" H 7200 3350 50 0000 C CNN
F 1 "CONN_01X02" V 7300 3200 50 0000 C CNN
F 2 "VN750PS_E_Vertical:Pin_Header_Straight_25x02" H 7200 3200 60 0001 C CNN
F 3 "" H 7200 3200 60 0000 C CNN
1 7200 3200
1 0 0 -1
$EndComp
$Comp
L CONN_01X08 P1
U 1 1 55A7E2A2
P 3550 3150
F 0 "P1" H 3550 3600 50 0000 C CNN
F 1 "CONN_01X08" V 3650 3150 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Angled_1x08" H 3550 3150 60 0001 C CNN
F 3 "" H 3550 3150 60 0000 C CNN
1 3550 3150
-1 0 0 1
$EndComp
Wire Wire Line
4900 3150 4750 3150
Wire Wire Line
4750 3150 4750 3050
Wire Wire Line
4750 3300 4900 3300
Wire Wire Line
4900 3450 4750 3450
Wire Wire Line
4750 3450 4750 3750
Wire Wire Line
6250 3300 6350 3300
Wire Wire Line
6350 3300 6350 3450
Wire Wire Line
6250 3450 7000 3450
Connection ~ 6350 3450
Wire Wire Line
6600 2700 6600 3150
Wire Wire Line
6250 3150 7000 3150
Wire Wire Line
6250 3600 6800 3600
Wire Wire Line
6800 3600 6800 3150
Connection ~ 6600 3150
Connection ~ 6800 3150
Wire Wire Line
7000 3450 7000 3250
Connection ~ 6600 3450
Wire Wire Line
4450 3050 4150 3050
Wire Wire Line
4150 3050 4150 3000
Wire Wire Line
4000 3100 4000 3300
Wire Wire Line
4000 3300 4450 3300
Connection ~ 4150 3050
Connection ~ 4750 3550
Wire Wire Line
3800 3750 4450 3750
Wire Wire Line
4350 2700 4350 3750
Connection ~ 4350 3750
Wire Wire Line
3900 3200 3900 3550
Wire Wire Line
3900 3550 4450 3550
Wire Wire Line
3750 3300 3800 3300
Wire Wire Line
3800 3300 3800 3750
Wire Wire Line
3900 3200 3750 3200
Wire Wire Line
4000 3100 3750 3100
Wire Wire Line
4150 3000 3750 3000
$Comp
L +5V #PWR03
U 1 1 55A810DA
P 4350 2700
F 0 "#PWR03" H 4350 2550 50 0001 C CNN
F 1 "+5V" H 4350 2840 50 0000 C CNN
F 2 "" H 4350 2700 60 0000 C CNN
F 3 "" H 4350 2700 60 0000 C CNN
1 4350 2700
1 0 0 -1
$EndComp
$EndSCHEMATC

23
hardware/rusefi_lib/VN750PS-E.kicad_mod Normal file
View File

@ -0,0 +1,23 @@
(module VN750PS-E (layer F.Cu) (tedit 55A7DB70)
(fp_text reference REF** (at 0.32374 3.66904) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VN750PS-E (at -0.03154 -4.44848) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -1.45542 -2.0066) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.0625)))
)
(fp_line (start -1.92532 -2.58064) (end 1.72468 -2.58064) (layer F.SilkS) (width 0.15))
(fp_line (start 1.72974 -2.5908) (end 1.72974 2.4092) (layer F.SilkS) (width 0.15))
(fp_line (start -1.92024 2.413) (end 1.72976 2.413) (layer F.SilkS) (width 0.15))
(fp_line (start -1.92024 -2.58826) (end -1.92024 2.41174) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.69772 -1.9491 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -2.69772 -0.6791 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -2.69772 0.5909 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -2.69772 1.8609 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 2.50228 1.8609 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 2.50228 0.5909 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 2.50228 -0.6791 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 2.50228 -1.9491 270) (size 0.51 1.3) (layers F.Cu F.Paste F.Mask))
)