From 83fab63d4dc060680051605da8dcf10fb1ee767c Mon Sep 17 00:00:00 2001 From: rusefillc Date: Fri, 15 Oct 2021 23:59:08 -0400 Subject: [PATCH] Better Windows build-in DFU #3338 those are needed for DFU to be able to verify --- .../Data_Base/STM32_Prog_DB_0x413.xml | 322 +++ .../Data_Base/STM32_Prog_DB_0x419.xml | 599 ++++++ .../Data_Base/STM32_Prog_DB_0x421.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x423.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x431.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x433.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x434.xml | 599 ++++++ .../Data_Base/STM32_Prog_DB_0x440.xml | 217 ++ .../Data_Base/STM32_Prog_DB_0x441.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x442.xml | 266 +++ .../Data_Base/STM32_Prog_DB_0x444.xml | 206 ++ .../Data_Base/STM32_Prog_DB_0x445.xml | 228 +++ .../Data_Base/STM32_Prog_DB_0x448.xml | 244 +++ .../Data_Base/STM32_Prog_DB_0x449.xml | 529 +++++ .../Data_Base/STM32_Prog_DB_0x450.xml | 1118 ++++++++++ .../Data_Base/STM32_Prog_DB_0x452.xml | 605 ++++++ .../Data_Base/STM32_Prog_DB_0x458.xml | 393 ++++ .../Data_Base/STM32_Prog_DB_0x463.xml | 396 ++++ .../Data_Base/STM32_Prog_DB_0x480.xml | 847 ++++++++ .../Data_Base/STM32_Prog_DB_0x483.xml | 656 ++++++ .../Data_Base/STM32_Prog_DB_0x500.xml | 1822 +++++++++++++++++ .../Data_Base/STM32_Prog_DB_0x501.xml | 1820 ++++++++++++++++ 22 files changed, 12847 insertions(+) create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x419.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x423.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x431.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x433.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x434.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x441.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x442.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x444.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x445.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x448.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x449.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x450.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x452.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x458.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x463.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x480.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x483.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x501.xml diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml new file mode 100644 index 0000000000..bc991e0600 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x413.xml @@ -0,0 +1,322 @@ + + + + 0x413 + STMicroelectronics + MCU + Cortex-M4 + STM32F405xx/F407xx/F415xx/F417xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x419.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x419.xml new file mode 100644 index 0000000000..c2ceb99b75 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x419.xml @@ -0,0 +1,599 @@ + + + + 0x419 + STMicroelectronics + MCU + Cortex-M4 + STM32F42xxx/F43xxx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP0 + + 0x10 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + nWRP12 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP12 + + 0x10 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + + + + + + Write Protection (Bank 1) + + + + + WRP0 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Write Protection (Bank 2) + + + + + WRP12 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + WRP12 + + 0x0 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml new file mode 100644 index 0000000000..44e672f85b --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x421.xml @@ -0,0 +1,396 @@ + + + + 0x421 + STMicroelectronics + MCU + Cortex-M4 + STM32F446xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x423.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x423.xml new file mode 100644 index 0000000000..ce444ee6d6 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x423.xml @@ -0,0 +1,396 @@ + + + + 0x423 + STMicroelectronics + MCU + Cortex-M4 + STM32F401xB/C + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x6 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0x6 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0x6 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0x6 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x431.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x431.xml new file mode 100644 index 0000000000..acd7d2af57 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x431.xml @@ -0,0 +1,396 @@ + + + + 0x431 + STMicroelectronics + MCU + Cortex-M4 + STM32F411xC/E + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x433.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x433.xml new file mode 100644 index 0000000000..6bdd4cb0ad --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x433.xml @@ -0,0 +1,396 @@ + + + + 0x433 + STMicroelectronics + MCU + Cortex-M4 + STM32F401xD/E + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0x8 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x434.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x434.xml new file mode 100644 index 0000000000..a0386f3018 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x434.xml @@ -0,0 +1,599 @@ + + + + 0x434 + STMicroelectronics + MCU + Cortex-M4 + STM32F469xx/F467xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP0 + + 0x10 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + nWRP12 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP12 + + 0x10 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP0 + + 0x0 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Write Protection + + + + + nWRP12 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + nWRP12 + + 0x0 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml new file mode 100644 index 0000000000..6409758821 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x440.xml @@ -0,0 +1,217 @@ + + + + 0x440 + STMicroelectronics + MCU + Cortex-M0 + STM32F05x/F030x8 + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP8 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x441.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x441.xml new file mode 100644 index 0000000000..a70525e381 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x441.xml @@ -0,0 +1,396 @@ + + + + 0x441 + STMicroelectronics + MCU + Cortex-M4 + STM32F412 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0xC + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0xC + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x442.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x442.xml new file mode 100644 index 0000000000..705c5e26e0 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x442.xml @@ -0,0 +1,266 @@ + + + + 0x442 + STMicroelectronics + MCU + Cortex-M0 + STM32F09x/F030xC + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x13 + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from main flash memory + + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + + + BOOT_SEL + + 0x17 + 0x1 + RW + + BOOT0 signal is defined by nBOOT0 option bit + BOOT0 signal is defined by BOOT0 pin value + + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP8 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + nWRP16 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP24 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x444.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x444.xml new file mode 100644 index 0000000000..19c7f6e0c9 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x444.xml @@ -0,0 +1,206 @@ + + + + 0x444 + STMicroelectronics + MCU + Cortex-M0 + STM32F03x + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + nBOOT1 + Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system flash when BOOT0=1 + + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x445.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x445.xml new file mode 100644 index 0000000000..442c1c6b53 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x445.xml @@ -0,0 +1,228 @@ + + + + 0x445 + STMicroelectronics + MCU + Cortex-M0 + STM32F04x/F070x6 + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x13 + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from main flash memory + + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system memory when BOOT0=1 + + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + + + BOOT_SEL + + 0x17 + 0x1 + RW + + BOOT0 signal is defined by nBOOT0 option bit + BOOT0 signal is defined by BOOT0 pin value + + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x448.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x448.xml new file mode 100644 index 0000000000..9fbafb603b --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x448.xml @@ -0,0 +1,244 @@ + + + + 0x448 + STMicroelectronics + MCU + Cortex-M0 + STM32F07x + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + nBOOT1 + Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system flash when BOOT0=1 + + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP8 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + nWRP16 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP24 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x449.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x449.xml new file mode 100644 index 0000000000..771429f1f1 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x449.xml @@ -0,0 +1,529 @@ + + + + 0x449 + STMicroelectronics + MCU + Cortex-M7 + STM32F74x/STM32F75x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x10 + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x10 + 0x2 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0xF + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0xE + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + + + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + + + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x0 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x450.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x450.xml new file mode 100644 index 0000000000..cbf48a72ae --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x450.xml @@ -0,0 +1,1118 @@ + + + + 0x450 + STMicroelectronics + MCU + Cortex-M7 + STM32H7xx + STM32H7 + ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Dual + 0x20 + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Dual + 0x20 + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + R + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + W + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + RSS + + + + + RSS1 + + 0x1A + 0x1 + R + + No SFI process on going + SFI process started + + + + + + + + + RSS1 + + 0x1A + 0x1 + W + + No SFI process on going + SFI process started + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. + 0x2 + 0x2 + R + + reset level is set to VBOR0 + reset level is set to VBOR1 + reset level is set to VBOR2 + reset level is set to VBOR3 + + + + + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. + 0x2 + 0x2 + W + + reset level is set to VBOR0 + reset level is set to VBOR1 + reset level is set to VBOR2 + reset level is set to VBOR3 + + + + + + + User Configuration + + + + + IWDG1_SW + + 0x4 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + IWDG2_SW + + 0x5 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP_D1 + + 0x6 + 0x1 + R + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY_D1 + + 0x7 + 0x1 + R + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + R + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + R + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + R + + Security feature disabled + Security feature enabled + + + + BCM4 + + 0x16 + 0x1 + R + + CM4 boot disabled + CM4 boot enabled + + + + BCM7 + + 0x17 + 0x1 + R + + CM7 boot disabled + CM7 boot enabled + + + + NRST_STOP_D2 + + 0x18 + 0x1 + R + + STOP mode on Domain 2 is entering with reset + STOP mode on Domain 2 is entering without reset + + + + NRST_STBY_D2 + + 0x19 + 0x1 + R + + STANDBY mode on Domain 2 is entering with reset + STANDBY mode on Domain 2 is entering without reset + + + + SWAP_BANK + + 0x1F + 0x1 + R + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + + + IO_HSLV + I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + IWDG1_SW + + 0x4 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + IWDG2_SW + + 0x5 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP_D1 + + 0x6 + 0x1 + W + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY_D1 + + 0x7 + 0x1 + W + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + W + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + W + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + W + + Security feature disabled + Security feature enabled + + + + IO_HSLV + I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + BCM4 + + 0x16 + 0x1 + W + + CM4 boot disabled + CM4 boot enabled + + + + BCM7 + + 0x17 + 0x1 + W + + CM7 boot disabled + CM7 boot enabled + + + + NRST_STOP_D2 + + 0x18 + 0x1 + W + + STOP mode on Domain 2 is entering with reset + STOP mode on Domain 2 is entering without reset + + + + NRST_STBY_D2 + + 0x19 + 0x1 + W + + STANDBY mode on Domain 2 is entering with reset + STANDBY mode on Domain 2 is entering without reset + + + + SWAP_BANK + + 0x1F + 0x1 + W + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + + + + + + Boot address Option Bytes + + + + + BOOT_CM7_ADD0 + Define the boot address for Cortex-M7 when BOOT0=0 + 0x0 + 0x10 + R + + + + BOOT_CM7_ADD1 + Define the boot address for Cortex-M7 when BOOT0=1 + 0x10 + 0x10 + R + + + + + + + + + BOOT_CM4_ADD0 + Define the boot address for Cortex-M4 when BOOT0=0 + 0x0 + 0x10 + R + + + + BOOT_CM4_ADD1 + Define the boot address for Cortex-M4 when BOOT0=1 + 0x10 + 0x10 + R + + + + + + + + + BOOT_CM7_ADD0 + + 0x0 + 0x10 + W + + + + BOOT_CM7_ADD1 + + 0x10 + 0x10 + W + + + + + + + + + BOOT_CM4_ADD0 + + 0x0 + 0x10 + W + + + + BOOT_CM4_ADD1 + + 0x10 + 0x10 + W + + + + + + + PCROP Protection + + + + + PROT_AREA_START1 + Flash Bank 1 PCROP start address + 0x0 + 0xC + R + + + + PROT_AREA_END1 + Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. + 0x10 + 0xC + R + + + + DMEP1 + + 0x1F + 0x1 + R + + Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START1 + Flash Bank 1 PCROP start address + 0x0 + 0xC + W + + + + PROT_AREA_END1 + Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + W + + + + DMEP1 + + 0x1F + 0x1 + W + + Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START2 + Flash Bank 2 PCROP start address + 0x0 + 0xC + R + + + + PROT_AREA_END2 + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + R + + + + DMEP2 + + 0x1F + 0x1 + R + + Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START2 + Flash Bank 2 PCROP start address + 0x0 + 0xC + W + + + + PROT_AREA_END2 + Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + W + + + + DMEP2 + + 0x1F + 0x1 + W + + Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + Secure Protection + + + + + SEC_AREA_START1 + Flash Bank 1 secure area start address + 0x0 + 0xC + R + + + + SEC_AREA_END1 + Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. + 0x10 + 0xC + R + + + + DMES1 + + 0x1F + 0x1 + R + + Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START1 + Flash Bank 1 secure area start address + 0x0 + 0xC + W + + + + SEC_AREA_END1 + Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. + 0x10 + 0xC + W + + + + DMES1 + + 0x1F + 0x1 + W + + Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START2 + Flash Bank 2 secure area start address + 0x0 + 0xC + R + + + + SEC_AREA_END2 + Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. + 0x10 + 0xC + R + + + + DMES2 + + 0x1F + 0x1 + R + + Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START2 + Flash Bank 2 secure area start address + 0x0 + 0xC + W + + + + SEC_AREA_END2 + Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. + 0x10 + 0xC + W + + + + DMES2 + + 0x1F + 0x1 + W + + Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + DTCM RAM Protection + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + R + + 2 KB + 4 KB + 8 KB + 16 KB + + + + + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + W + + 2 KB + 4 KB + 8 KB + 16 KB + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + R + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x0 + 0x1 + R + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + nWRP0 + + 0x0 + 0x8 + W + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x0 + 0x1 + W + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + nWRP8 + + 0x0 + 0x8 + R + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + nWRP8 + + 0x0 + 0x8 + W + + Write protection active on this sector + Write protection not active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x452.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x452.xml new file mode 100644 index 0000000000..8b0454c451 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x452.xml @@ -0,0 +1,605 @@ + + + + 0x452 + STMicroelectronics + MCU + Cortex-M7 + STM32F72x/STM32F73x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x10 + + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x10 + + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x10 + 0x4 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + Read/Write Protection + + + + + PCROP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on this sector + PCROP protection active on this sector + + + + PCROP0 + + 0x0 + 0x4 + RW + + PCROP protection not active on this sector + PCROP protection active on this sector + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0xF + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0xE + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + + + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + + + PCROP_RDP + + 0xF + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + + + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x0 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + + + + + + Read/Write Protection + + + + + PCROP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on this sector + PCROP protection active on this sector + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x458.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x458.xml new file mode 100644 index 0000000000..0e24985f71 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x458.xml @@ -0,0 +1,393 @@ + + + + 0x458 + STMicroelectronics + MCU + Cortex-M4 + STM32F410 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x5 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0x5 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0x5 + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0x5 + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x463.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x463.xml new file mode 100644 index 0000000000..1496544845 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x463.xml @@ -0,0 +1,396 @@ + + + + 0x463 + STMicroelectronics + MCU + Cortex-M4 + STM32F413/F423 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0xF + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x10 + 0xF + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0xF + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Write Protection + + + + + WRP0 + + 0x0 + 0xF + RW + + Write protection active + Write protection not active + + + + WRP0 + + 0x0 + 0xF + RW + + PCROP protection not active on sector i + PCROP protection active on sector i + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x480.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x480.xml new file mode 100644 index 0000000000..b88f5bc3bd --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x480.xml @@ -0,0 +1,847 @@ + + + + 0x480 + STMicroelectronics + MCU + Cortex-M7 + STM32H7A/B + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Dual + 0x20 + + + + + + + + + + + + + + + + Dual + 0x20 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + R + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + W + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + R + + reset level OFF + reset level is set to 2.1 V + reset level is set to 2.4 V + reset level is set to 2.7 V + + + + + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + W + + reset level OFF + reset level is set to 2.1 V + reset level is set to 2.4 V + reset level is set to 2.7 V + + + + + + + User Configuration + + + + + IWDG1_SW + + 0x4 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + R + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + VDDMMC_HSLV + + 0x10 + 0x1 + R + + I/O speed optimization at low-voltage disabled + VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + R + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + R + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + R + + Security feature disabled + Security feature enabled + + + + VDDIO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range,I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed + + + + SWAP_BANK_OPT + + 0x1F + 0x1 + R + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + + + + + + + + IWDG1_SW + + 0x4 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + W + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + VDDMMC_HSLV + + 0x10 + 0x1 + W + + I/O speed optimization at low-voltage disabled + VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + W + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + W + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + W + + Security feature disabled + Security feature enabled + + + + VDDIO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range,I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed + + + + SWAP_BANK_OPT + + 0x1F + 0x1 + W + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + + + + + + Boot address Option Bytes + + + + + BOOT_CM7_ADD0 + Define the boot address for Cortex-M7 when BOOT0=0 + 0x0 + 0x10 + R + + + + BOOT_CM7_ADD1 + Define the boot address for Cortex-M7 when BOOT0=1 + 0x10 + 0x10 + R + + + + + + + + + BOOT_CM7_ADD0 + + 0x0 + 0x10 + W + + + + BOOT_CM7_ADD1 + + 0x10 + 0x10 + W + + + + + + + PCROP Protection + + + + + PROT_AREA_START1 + Flash Bank 1 PCROP start address + 0x0 + 0xC + R + + + + PROT_AREA_END1 + Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. + 0x10 + 0xC + R + + + + DMEP1 + + 0x1F + 0x1 + R + + Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START1 + Flash Bank 1 PCROP start address + 0x0 + 0xC + W + + + + PROT_AREA_END1 + Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + W + + + + DMEP1 + + 0x1F + 0x1 + W + + Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START2 + Flash Bank 2 PCROP start address + 0x0 + 0xC + R + + + + PROT_AREA_END2 + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + R + + + + DMEP2 + + 0x1F + 0x1 + R + + Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START2 + Flash Bank 2 PCROP start address + 0x0 + 0xC + W + + + + PROT_AREA_END2 + Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + W + + + + DMEP2 + + 0x1F + 0x1 + W + + Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + Secure Protection + + + + + SEC_AREA_START1 + Flash Bank 1 secure area start address + 0x0 + 0xC + R + + + + SEC_AREA_END1 + Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. + 0x10 + 0xC + R + + + + DMES1 + + 0x1F + 0x1 + R + + Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START1 + Flash Bank 1 secure area start address + 0x0 + 0xC + W + + + + SEC_AREA_END1 + Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. + 0x10 + 0xC + W + + + + DMES1 + + 0x1F + 0x1 + W + + Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START2 + Flash Bank 2 secure area start address + 0x0 + 0xC + R + + + + SEC_AREA_END2 + Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. + 0x10 + 0xC + R + + + + DMES2 + + 0x1F + 0x1 + R + + Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START2 + Flash Bank 2 secure area start address + 0x0 + 0xC + W + + + + SEC_AREA_END2 + Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. + 0x10 + 0xC + W + + + + DMES2 + + 0x1F + 0x1 + W + + Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + DTCM RAM Protection + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + R + + 2 KB + 4 KB + 8 KB + 16 KB + + + + + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + W + + 2 KB + 4 KB + 8 KB + 16 KB + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x20 + R + + Write protection active + Write protection not active + + + + + + + + + nWRP0 + + 0x0 + 0x20 + W + + Write protection active + Write protection not active + + + + + + + + + nWRP32 + + 0x0 + 0x20 + R + + Write protection active + Write protection not active + + + + + + + + + nWRP32 + + 0x0 + 0x20 + W + + Write protection active + Write protection not active + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x483.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x483.xml new file mode 100644 index 0000000000..97456938bb --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x483.xml @@ -0,0 +1,656 @@ + + + + 0x483 + STMicroelectronics + MCU + Cortex-M7 + STM32H72x/STM32H73x + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + R + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + W + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + R + + BOR OFF + BOR level1: 2.1V + BOR level2: 2.4 V + BOR level3: 2.7 V + + + + + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + W + + reset level is set to 0.0 V + reset level is set to 2.1 V + reset level is set to 2.4 V + reset level is set to 2.7 V + + + + + + + User Configuration + + + + + IWDG1_SW + + 0x4 + 0x1 + R + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + R + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + R + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + R + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + R + + Security feature disabled + Security feature enabled + + + + + + + + + IWDG1_SW + + 0x4 + 0x1 + W + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + + + NRST_STBY + + 0x7 + 0x1 + W + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + + + IO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + FZ_IWDG_STOP + + 0x11 + 0x1 + W + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + W + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + + + SECURITY + + 0x15 + 0x1 + W + + Security feature disabled + Security feature enabled + + + + SWAP_BANK_OPT + + 0x1F + 0x1 + W + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + + + + + + Boot address Option Bytes + + + + + BOOT_CM7_ADD0 + Define the boot address for Cortex-M7 when BOOT0=0 + 0x0 + 0x10 + R + + + + BOOT_CM7_ADD1 + Define the boot address for Cortex-M7 when BOOT0=1 + 0x10 + 0x10 + R + + + + + + + + + BOOT_CM7_ADD0 + + 0x0 + 0x10 + W + + + + BOOT_CM7_ADD1 + + 0x10 + 0x10 + W + + + + + + + PCROP Protection + + + + + PROT_AREA_START + Flash Bank PCROP start address + 0x0 + 0xC + R + + + + PROT_AREA_END + Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address. + 0x10 + 0xC + R + + + + DMEP + + 0x1F + 0x1 + R + + Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + PROT_AREA_START + Flash Bank PCROP start address + 0x0 + 0xC + W + + + + PROT_AREA_END + Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + W + + + + DMEP + + 0x1F + 0x1 + W + + Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + Secure Protection + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + R + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + W + + 2 KB reserved to ST code + 4 KB reserved to ST code + 8 KB reserved to ST code + 16 KB reserved to ST code + + + + + + + + + SEC_AREA_START + Flash secure area start address + 0x0 + 0xC + R + + + + SEC_AREA_END + Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. + 0x10 + 0xC + R + + + + DMES + + 0x1F + 0x1 + R + + Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + + + SEC_AREA_START + Flash secure area start address + 0x0 + 0xC + W + + + + SEC_AREA_END + Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. + 0x10 + 0xC + W + + + + DMES + + 0x1F + 0x1 + W + + Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + nWRP0 + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + TCM_AXI Shared Configuration + + + + + TCM_AXI_SHARED + + 0x0 + 0x2 + R + + 64 KB ITCM : 320KB system AXI + 128KB ITCM : 256KB system AXI + 192KB ITCM : 192KB system AXI + 256KB ITCM : 128KB system AXI + + + + CPU_FREQ_BOOST + + 0x2 + 0x1 + R + + Feature disabled + CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) + + + + + + + + + TCM_AXI_SHARED + + 0x0 + 0x2 + W + + 64KB ITCM : 320KB system AXI + 128KB ITCM : 256KB system AXI + 192KB ITCM : 192KB system AXI + 256KB ITCM : 128KB system AXI + + + + CPU_FREQ_BOOST + + 0x2 + 0x1 + W + + Feature disabled + CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml new file mode 100644 index 0000000000..6b190d7370 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x500.xml @@ -0,0 +1,1822 @@ + + + + 0x500 + STMicroelectronics + MPU + Cortex-A7 + STM32MP1 + STM32MP + ARM 32-bit Cortex-A7 and ARM 32-bit Cortex-M4 dualprocessor based device, CPU clock up to 600MHz + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + + Single + + + + + + + + + OTP Memory + Configuration + + RW + + + + OTP + + + + + none + none + 0x0 + 0x20 + R + + + + + + + + TR + set SAFMEM Ring current level, default value = 0b00 + 0x7 + 0x2 + RW + + + PRGWIDTH + SAFMEM Programming Pulse Width, default value = 0b0001 + 0x3 + 0x4 + RW + + + FRC + SAFMEM CLOCK frequency range selection, default value = 0b11 + 0x1 + 0x2 + RW + + + PWRUP + SAFMEM Power up control + 0x0 + 0x1 + RW + + + + + + + + BIST2LOCK + 0: BIST2 is not locked, 1: BIST2 is locked. + 0x7 + 0x1 + R + + + BIST1LOCK + 0: BIST1 is not locked, 1: BIST1 is locked. + 0x6 + 0x1 + R + + + PWRON + 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. + 0x5 + 0x1 + R + + + PROGFAIL + 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. + 0x4 + 0x1 + R + + + BUSY + 0: SAFMEM is Idle, 1: SAFMEM operation is on going. + 0x3 + 0x1 + R + + + INVALID + 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. + 0x2 + 0x1 + R + + + FULLDBG + 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. + 0x1 + 0x1 + R + + + SECURE + 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. + 0x0 + 0x1 + R + + + + + + + + GPLOCK + 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. + 0x4 + 0x1 + RW + + + FENREG + 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. + 0x3 + 0x1 + RW + + + DENREG + 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. + 0x2 + 0x1 + RW + + + OTP + 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. + 0x0 + 0x1 + RW + + + + + + + + DBGSWENABLE + Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. + 0xA + 0x1 + RW + + + CFGSDISABLE + Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. + 0x9 + 0x1 + RW + + + CP15SDISABLE + Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. + 0x7 + 0x2 + RW + + + SPNIDEN + Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. + 0x6 + 0x1 + RW + + + SPIDEN + Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. + 0x5 + 0x1 + RW + + + HDPEN + Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. + 0x4 + 0x1 + RW + + + DEVICEEN + Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. + 0x3 + 0x1 + RW + + + NIDEN + Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. + 0x2 + 0x1 + RW + + + DBGEN + Debug enable with signal dbgen. 0: Disabled, 1: Enabled. + 0x1 + 0x1 + RW + + + DFTEN + DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. + 0x0 + 0x1 + RW + + + + + + + + CAN_disable + 0: CAN interface is enabled, 1: CAN interface is disabled. + 0x3 + 0x1 + RW + + + GPU_disable + 0: GPU enabled, 1: GPU disabled. + 0x2 + 0x1 + RW + + + Dual_A7_disable + 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. + 0x1 + 0x1 + RW + + + Crypto_disable + 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. + 0x0 + 0x1 + RW + + + + + + + + W_R conf + This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM + 0x0 + 0x1 + RW + + + + + + + + BSEC_OTP_DISTURBED0 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_DISTURBED1 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_DISTURBED2 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR0 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR1 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR2 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_WRLOCK0 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_WRLOCK1 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_WRLOCK2 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK0 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK1 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK2 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK0 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK1 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK2 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK0 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK1 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK2 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + CFG0 + These bits determins the OTP mode encoding + 0x0 + 0x7 + RW + + + + + + + + fdis3 + Disable CAN + 0x3 + 0x1 + RW + + + fdis2 + Disable GPU + 0x2 + 0x1 + RW + + + fdis1 + Disable CPU1 + 0x1 + 0x1 + RW + + + fdis0 + Disable Crypto (license export) + 0x0 + 0x1 + RW + + + + + + + + rma_force + RMA force Bit + 0x0 + 0x1 + RW + + + rma_relock + RMA relock Bit + 0x1 + 0x1 + RW + + + + + + + + CFG3 + These bits determins the BOOT source definition + 0x0 + 0x20 + RW + + + + + + + + CFG4 + These bits determins the BOOT monotonic counter + 0x0 + 0x20 + RW + + + + + + + + CFG5 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG6 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG7 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG8 + BOOT/Device configuration. + 0x2 + 0x1E + RW + + + rma_relock + RMA relock Bit + 0x1 + 0x1 + RW + + + rma_lock + RMA lock Bit + 0x0 + 0x1 + RW + + + + + + + + CFG9 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG10 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG11 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG12 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + ID0 + Lot ID on 42bit (11LSB's) + 0x15 + 0xB + RW + + + ID0 + Wafer ID + 0x10 + 0x5 + RW + + + ID0 + Wafer Y coordinates + 0x8 + 0x8 + RW + + + ID0 + Wafer X coordinates + 0x0 + 0x8 + RW + + + + + + + + ID1 + Lot ID on 42bit (31MSB's) + 0x0 + 0x20 + RW + + + + + + + + ID2 + Test program flow T[12],F[12],Q[12] + 0x14 + 0xC + RW + + + ID2 + FT program revision + 0xA + 0xA + RW + + + ID2 + EWS program revision + 0x0 + 0xA + RW + + + + + + + + HW0 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW1 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW2 + Analog TRIM and hardware options + 0x0 + 0x20 + RW + + + + + + + + HW3 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW4 + not used yet + 0x0 + 0x20 + RW + + + + + + + + HW5 + memory repair bits + 0x0 + 0x20 + RW + + + + + + + + HW6 + memory repair bits + 0x0 + 0x20 + RW + + + + + + + + HW7 + reserved + 0x0 + 0x20 + RW + + + + + + + + PKH0 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH1 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH2 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH3 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH4 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH5 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH6 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH7 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + XK0 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK1 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK2 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK3 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK4 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK5 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK6 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK7 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK8 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK9 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK10 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK11 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK12 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK13 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK14 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK15 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK16 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK17 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK18 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK19 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK20 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK21 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK22 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK23 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK24 + RMA lock and relock passwords + 0x0 + 0x20 + RW + + + + + + + + XK25 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK26 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK27 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK28 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK29 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK30 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK31 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK32 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK33 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK34 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK35 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK36 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK37 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK38 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK39 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK40 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK41 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK42 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK43 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK44 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK45 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK46 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK47 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK48 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK49 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK50 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK51 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK52 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK53 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK54 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK55 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK56 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK57 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK58 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK59 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK60 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK61 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK62 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK63 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + ECC_USE + SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. + 0x4 + 0x4 + R + + + SAFMEM_SIZE + SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. + 0x0 + 0x4 + R + + + + + + + + MAJREV + IP Version major revision information. + 0x4 + 0x4 + R + + + MINREV + IP Version minor revision information. + 0x0 + 0x4 + R + + + + + + + + ID + IP Identification. + 0x0 + 0x20 + R + + + + + + + + ID + IP Magic Identification. + 0x0 + 0x20 + R + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x501.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x501.xml new file mode 100644 index 0000000000..2e866a6dc3 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x501.xml @@ -0,0 +1,1820 @@ + + + + 0x501 + STMicroelectronics + MPU + Cortex-A7 + STM32MP13xx + STM32MP + ARM 32-bit Cortex-A7 based device, CPU clock up to 600MHz + + + + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + + Single + + + + + + + + + OTP Memory + Configuration + + RW + + + + OTP + + + + + none + none + 0x0 + 0x20 + R + + + + + + + + TR + set SAFMEM Ring current level, default value = 0b00 + 0x7 + 0x2 + RW + + + PRGWIDTH + SAFMEM Programming Pulse Width, default value = 0b0001 + 0x3 + 0x4 + RW + + + FRC + SAFMEM CLOCK frequency range selection, default value = 0b11 + 0x1 + 0x2 + RW + + + PWRUP + SAFMEM Power up control + 0x0 + 0x1 + RW + + + + + + + + BIST2LOCK + 0: BIST2 is not locked, 1: BIST2 is locked. + 0x7 + 0x1 + R + + + BIST1LOCK + 0: BIST1 is not locked, 1: BIST1 is locked. + 0x6 + 0x1 + R + + + PWRON + 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. + 0x5 + 0x1 + R + + + PROGFAIL + 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. + 0x4 + 0x1 + R + + + BUSY + 0: SAFMEM is Idle, 1: SAFMEM operation is on going. + 0x3 + 0x1 + R + + + INVALID + 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. + 0x2 + 0x1 + R + + + FULLDBG + 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. + 0x1 + 0x1 + R + + + SECURE + 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. + 0x0 + 0x1 + R + + + + + + + + GPLOCK + 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. + 0x4 + 0x1 + RW + + + FENREG + 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. + 0x3 + 0x1 + RW + + + DENREG + 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. + 0x2 + 0x1 + RW + + + OTP + 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. + 0x0 + 0x1 + RW + + + + + + + + DBGSWENABLE + Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. + 0xA + 0x1 + RW + + + CFGSDISABLE + Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. + 0x9 + 0x1 + RW + + + CP15SDISABLE + Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. + 0x7 + 0x2 + RW + + + SPNIDEN + Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. + 0x6 + 0x1 + RW + + + SPIDEN + Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. + 0x5 + 0x1 + RW + + + HDPEN + Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. + 0x4 + 0x1 + RW + + + DEVICEEN + Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. + 0x3 + 0x1 + RW + + + NIDEN + Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. + 0x2 + 0x1 + RW + + + DBGEN + Debug enable with signal dbgen. 0: Disabled, 1: Enabled. + 0x1 + 0x1 + RW + + + DFTEN + DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. + 0x0 + 0x1 + RW + + + + + + + + CAN_disable + 0: CAN interface is enabled, 1: CAN interface is disabled. + 0x3 + 0x1 + RW + + + GPU_disable + 0: GPU enabled, 1: GPU disabled. + 0x2 + 0x1 + RW + + + Dual_A7_disable + 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. + 0x1 + 0x1 + RW + + + Crypto_disable + 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. + 0x0 + 0x1 + RW + + + + + + + + W_R conf + This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM + 0x0 + 0x1 + RW + + + + + + + + BSEC_OTP_DISTURBED0 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_DISTURBED1 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_DISTURBED2 + If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR0 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR1 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_ERROR2 + If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. + 0x0 + 0x20 + R + + + + + + + + BSEC_OTP_WRLOCK0 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_WRLOCK1 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_WRLOCK2 + If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK0 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK1 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SPLOCK2 + If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK0 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK1 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SWLOCK2 + If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK0 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK1 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + BSEC_OTP_SRLOCK2 + If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register + 0x0 + 0x20 + RW + + + + + + + + CFG0 + These bits determins the OTP mode encoding + 0x0 + 0x7 + RW + + + + + + + + fdis3 + Disable CAN + 0x3 + 0x1 + RW + + + fdis2 + Disable GPU + 0x2 + 0x1 + RW + + + fdis1 + Disable CPU1 + 0x1 + 0x1 + RW + + + fdis0 + Disable Crypto (license export) + 0x0 + 0x1 + RW + + + + + + + + rma_force + RMA force Bit + 0x0 + 0x1 + RW + + + rma_relock + RMA relock Bit + 0x1 + 0x1 + RW + + + + + + + + CFG3 + These bits determins the BOOT source definition + 0x0 + 0x20 + RW + + + + + + + + CFG4 + These bits determins the BOOT monotonic counter + 0x0 + 0x20 + RW + + + + + + + + CFG5 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG6 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG7 + These bits determins the BOOT AFmux configuration + 0x0 + 0x20 + RW + + + + + + + + CFG8 + BOOT/Device configuration. + 0x2 + 0x1E + RW + + + rma_relock + RMA relock Bit + 0x1 + 0x1 + RW + + + rma_lock + RMA lock Bit + 0x0 + 0x1 + RW + + + + + + + + CFG9 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG10 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG11 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + CFG12 + These bits determin the device configuration. + 0x0 + 0x20 + RW + + + + + + + + ID0 + Lot ID on 42bit (11LSB's) + 0x15 + 0xB + RW + + + ID0 + Wafer ID + 0x10 + 0x5 + RW + + + ID0 + Wafer Y coordinates + 0x8 + 0x8 + RW + + + ID0 + Wafer X coordinates + 0x0 + 0x8 + RW + + + + + + + + ID1 + Lot ID on 42bit (31MSB's) + 0x0 + 0x20 + RW + + + + + + + + ID2 + Test program flow T[12],F[12],Q[12] + 0x14 + 0xC + RW + + + ID2 + FT program revision + 0xA + 0xA + RW + + + ID2 + EWS program revision + 0x0 + 0xA + RW + + + + + + + + HW0 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW1 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW2 + Analog TRIM and hardware options + 0x0 + 0x20 + RW + + + + + + + + HW3 + Analog TRIM + 0x0 + 0x20 + RW + + + + + + + + HW4 + not used yet + 0x0 + 0x20 + RW + + + + + + + + HW5 + memory repair bits + 0x0 + 0x20 + RW + + + + + + + + HW6 + memory repair bits + 0x0 + 0x20 + RW + + + + + + + + HW7 + reserved + 0x0 + 0x20 + RW + + + + + + + + PKH0 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH1 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH2 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH3 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH4 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH5 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH6 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + PKH7 + Public Key Hash + 0x0 + 0x20 + RW + + + + + + + + XK0 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK1 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + + + + + + + + XK2 + ST ECDSA Private Key for SSP + 0x0 + 0x20 + RW + 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+ + + + + + XK16 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK17 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK18 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK19 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK20 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK21 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK22 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK23 + ST Public ECDSA Chip Certificate for SSP + 0x0 + 0x20 + RW + + + + + + + + XK24 + RMA lock and relock passwords + 0x0 + 0x20 + RW + + + + + + + + XK25 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK26 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK27 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK28 + OEM OTP secret word + 0x0 + 0x20 + RW + + + + + + + + XK29 + OEM OTP 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