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custom-board-bundle-sample-fork-of-rusefi
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update h7 clock config (#2388) 

* h7 clocks

* run the core at 400

* disable LSE

* 8mhz timer clock

* osc

* it has to be even slower

* something is wrong with WFI

* this was wrong anyway
This commit is contained in:
Matthew Kennedy 2021-02-23 17:55:38 -10:00 committed by GitHub
parent 8bf8c93c4e
commit 86233c4e62
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 31 additions and 25 deletions
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4
firmware/hw_layer/ports/stm32/port_mpu_util.h
View File

@ -12,9 +12,9 @@
#define MCU_SERIAL_NUMBER_BYTES 12
// 12mhz was chosen because it's the GCD of (168, 180, 216), the three speeds of STM32 currently supported
// 4mhz was chosen because it's the GCD of (84, 108, 200), the three speeds of STM32 TIM5 clock currently supported
// https://www.wolframalpha.com/input/?i=common+factors+of+168+180+216
#define US_TO_NT_MULTIPLIER (12)
#define US_TO_NT_MULTIPLIER (4)
// Scheduler queue timer - use TIM5
#define SCHEDULER_PWM_DEVICE PWMD5

5
firmware/hw_layer/ports/stm32/serial_over_usb/usbconsole.c
View File

@ -23,6 +23,9 @@ static bool isUsbSerialInitialized = false;
void usb_serial_start(void) {
usbPopulateSerialNumber(MCU_SERIAL_NUMBER_LOCATION, MCU_SERIAL_NUMBER_BYTES);
efiSetPadMode("USB DM", EFI_USB_SERIAL_DM, PAL_MODE_ALTERNATE(EFI_USB_AF));
efiSetPadMode("USB DP", EFI_USB_SERIAL_DP, PAL_MODE_ALTERNATE(EFI_USB_AF));
/*
* Initializes a serial-over-USB CDC driver.
*/
@ -43,8 +46,6 @@ void usb_serial_start(void) {
usbConnectBus(serusbcfg.usbp);
#if HAL_USE_SERIAL
efiSetPadMode("USB DM", EFI_USB_SERIAL_DM, PAL_MODE_ALTERNATE(EFI_USB_AF));
efiSetPadMode("USB DP", EFI_USB_SERIAL_DP, PAL_MODE_ALTERNATE(EFI_USB_AF));
/*
* Activates the serial driver using the driver default configuration.
*/

5
firmware/hw_layer/ports/stm32/stm32h7/board.h
View File

@ -69,7 +69,12 @@
#define STM32_HSECLK 8000000U
#endif
// Nucleo boards use MCO signal from St-Link and NOT oscillator - these need STM32_HSE_BYPASS
// if you do not have Sl-Link and MCO on your board, you need EFI_USE_OSC
#ifndef EFI_USE_OSC
#define STM32_HSE_BYPASS
#endif /* EFI_USE_OSC */
/*
* MCU type as defined in the ST header.

2
firmware/hw_layer/ports/stm32/stm32h7/cfg/chconf.h
View File

@ -717,7 +717,7 @@
* @brief Sleep at idle.
* @details This option enables call to __WFI() from idle thread to save power.
*/
#define CORTEX_ENABLE_WFI_IDLE TRUE
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif /* CHCONF_H */

40
firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h
View File

@ -74,7 +74,7 @@
#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
/*
@ -91,35 +91,35 @@
#define STM32_PLL1_DIVN_VALUE 400
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 16
#define STM32_PLL1_DIVR_VALUE 8
#define STM32_PLL1_DIVQ_VALUE 4
#define STM32_PLL1_DIVR_VALUE 2
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE
#define STM32_PLL2_R_ENABLED TRUE
#define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_DIVN_VALUE 480
#define STM32_PLL2_FRACN_VALUE 0
#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL2_DIVP_VALUE 10
#define STM32_PLL2_DIVQ_VALUE 12
#define STM32_PLL2_DIVR_VALUE 2
#define STM32_PLL3_ENABLED TRUE
#define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 400
#define STM32_PLL3_DIVN_VALUE 480
#define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 8
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 20
#define STM32_PLL3_DIVR_VALUE 12
/*
* Core clocks dynamic settings (can be changed at runtime).
* Reading STM32 Reference Manual is required.
*/
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_RTCSEL STM32_RTCSEL_LSI_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
@ -145,24 +145,24 @@
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1
#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
#define STM32_FDCANSEL STM32_FDCANSEL_PLL2_Q_CK
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PLL2_Q_CK
#define STM32_SPI123SEL STM32_SPI123SEL_PLL2_P_CK
#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE_CK
#define STM32_USBSEL STM32_USBSEL_HSI48_CK
#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
#define STM32_USART16SEL STM32_USART16SEL_PCLK2
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
#define STM32_USART16SEL STM32_USART16SEL_PLL2_Q_CK
#define STM32_USART234578SEL STM32_USART234578SEL_PLL2_Q_CK
#define STM32_SPI6SEL STM32_SPI6SEL_PLL2_Q_CK
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4