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custom-board-bundle-sample-fork-of-rusefi
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rusefi 2019-01-09 23:29:24 -05:00
parent cbd2d69731
commit a0caf91011
3 changed files with 9 additions and 82 deletions
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hardware/Power_regulator_TPS54340/gerber/TPS54340_Buck_Regulator_R0.1.zip Normal file
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73
hardware/TLE8110ED_breakout_board/TLE8110ED.lib
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@ -1,73 +0,0 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# TLE8110ED
#
DEF TLE8110ED U 0 40 Y Y 1 F N
F0 "U" 0 50 60 H V C CNN
F1 "TLE8110ED" 0 -150 60 H V C CNN
F2 "" 0 50 60 H I C CNN
F3 "" 0 50 60 H I C CNN
DRAW
S -700 1350 650 -1450 0 1 0 N
X GND1 1 -400 -1650 200 U 50 50 1 1 W
X In1 2 -900 1250 200 R 50 50 1 1 I
X In2 3 -900 1100 200 R 50 50 1 1 I
X EN 4 -900 -350 200 R 50 50 1 1 I
X ~RST 5 -900 -500 200 R 50 50 1 1 I
X In3 6 -900 950 200 R 50 50 1 1 I
X In4 7 -900 800 200 R 50 50 1 1 I
X VDD 8 -900 -1050 200 R 50 50 1 1 W
X In5 9 -900 650 200 R 50 50 1 1 I
X VCC 10 -900 -1200 200 R 50 50 1 1 W
X Out9 20 850 50 200 L 50 50 1 1 O
X Out1 30 850 1250 200 L 50 50 1 1 O
X S_SO 11 850 -400 200 L 50 50 1 1 O
X Out10 21 850 -100 200 L 50 50 1 1 O
X Out5 31 850 650 200 L 50 50 1 1 O
X S_CLK 12 850 -550 200 L 50 50 1 1 I
X N.C. 22 -900 -700 200 R 50 50 1 1 N
X GND6 32 350 -1650 200 U 50 50 1 1 W
X S_CS 13 850 -700 200 L 50 50 1 1 I
X GND5 23 200 -1650 200 U 50 50 1 1 W
X N.C. 33 -900 -850 200 R 50 50 1 1 N
X S_SI 14 850 -850 200 L 50 50 1 1 I
X Out6 24 850 500 200 L 50 50 1 1 O
X Out8 34 850 200 200 L 50 50 1 1 O
X In6 15 -900 500 200 R 50 50 1 1 I
X Out4 25 850 800 200 L 50 50 1 1 O
X Out7 35 850 350 200 L 50 50 1 1 O
X In7 16 -900 350 200 R 50 50 1 1 I
X Out3 26 850 950 200 L 50 50 1 1 O
X GND4 36 50 -1650 200 U 50 50 1 1 W
X In8 17 -900 200 200 R 50 50 1 1 I
X In9 27 -900 50 200 R 50 50 1 1 I
X GND_chass 37 550 -1650 200 U 50 50 1 1 W
X GND2 18 -250 -1650 200 U 50 50 1 1 W
X In10 28 -900 -100 200 R 50 50 1 1 I
X GND3 19 -100 -1650 200 U 50 50 1 1 W
X Out2 29 850 1100 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# TPS3839DQN
#
DEF TPS3839DQN U 0 10 Y Y 1 F N
F0 "U" 100 350 50 H V L CNN
F1 "TPS3839DQN" 100 250 50 H V L CNN
F2 "Housings_SON:X2SON-4_1x1mm_Pitch0.65mm" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
X2SON*1x1mm*Pitch0.65mm*
$ENDFPLIST
DRAW
S -100 200 300 -200 0 1 10 f
X ~RESET 1 400 0 100 L 50 50 1 1 O
X NC 2 -100 0 100 R 50 50 1 1 N N
X GND 3 0 -300 100 U 50 50 1 1 W
X VDD 4 0 300 100 D 50 50 1 1 W
X TP 5 100 -300 100 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
#End Library

18
hardware/TLE8110ED_breakout_board/TLE8110ED.pro
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@ -1,4 +1,4 @@
update=1/8/2019 6:45:32 PM update=1/9/2019 5:29:23 AM
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -27,14 +27,6 @@ SolderMaskMinWidth=0
DrawSegmentWidth=0.2 DrawSegmentWidth=0.2
BoardOutlineThickness=0.09999999999999999 BoardOutlineThickness=0.09999999999999999
ModuleOutlineThickness=0.15 ModuleOutlineThickness=0.15
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=TLE8110ED
LibName2=conn
LibName3=mechanical
LibName4=power
[schematic_editor] [schematic_editor]
version=1 version=1
PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
@ -45,3 +37,11 @@ NetFmtName=
SpiceForceRefPrefix=0 SpiceForceRefPrefix=0
SpiceUseNetNumbers=0 SpiceUseNetNumbers=0
LabSize=60 LabSize=60
[eeschema]
version=1
LibDir=../rusefi_lib
[eeschema/libraries]
LibName1=conn
LibName2=mechanical
LibName3=power
LibName4=TLE8110ED