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MC33816 default firmware

This commit is contained in:
rusefi 2019-12-26 23:06:31 -05:00
parent 8bc2dba054
commit a9229d08cb
19 changed files with 1486 additions and 0 deletions
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198
firmware/hw_layer/mc33816/rusefi/Logic_Wave/wave_list.do Normal file
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<Waves>
<Divider>
<Name>STARTx</Name>
</Divider>
<Wave>
<Name>Start1</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>8</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start2</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>9</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start3</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>10</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start4</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>11</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start5</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>12</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start6</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>13</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Start7</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>14</Ordinal>
<Direction>Input</Direction>
<Radix>Decimal</Radix>
</Wave>
<Divider>
<Name>INJ1</Name>
</Divider>
<Wave>
<Name>Hs1Command</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>6</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Hs2Command</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>7</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Ls1Command</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>13</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>CurrentFeedback1</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>0</Ordinal>
<Direction>Internal</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>FeedbackHs1Vds</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>10</Ordinal>
<Direction>Internal</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>FeedbackHs1Vsrc</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>11</Ordinal>
<Direction>Internal</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>FeedbackLs1Vds</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>24</Ordinal>
<Direction>Internal</Direction>
<Radix>Decimal</Radix>
</Wave>
<Divider>
<Name>DCDC</Name>
</Divider>
<Wave>
<Name>BoostFeedback</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>35</Ordinal>
<Direction>Internal</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Ls7Command</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>19</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Ls8Command</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>20</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>Flag0Out</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>4</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Divider>
<Name>DEBUG</Name>
</Divider>
<Wave>
<Name>Irq</Name>
<Path>
<PathElement>PT2000</PathElement>
</Path>
<Ordinal>5</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
<Wave>
<Name>irqSource</Name>
<Path>
<PathElement>PT2000</PathElement>
<PathElement>Injection Channel 1</PathElement>
<PathElement>ChSequencers</PathElement>
<PathElement>MicroMachineSeq0</PathElement>
<PathElement>UProgramCounter</PathElement>
</Path>
<Ordinal>7</Ordinal>
<Direction>Output</Direction>
<Radix>Decimal</Radix>
</Wave>
</Waves>

202
firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc Normal file
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********************************************************************************
* Example Code
*
* Copyright(C) 2019 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* NXP products. This software is supplied "AS IS" without any warranties
* of any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights
* under any patent, copyright, mask work right, or any other intellectual
* property rights in or to any products. NXP Semiconductors reserves the
* right to make changes in the software without notification. NXP
* Semiconductors also makes no representation or warranty that such
* application will be suitable for the specified use without further testing
* or modification.
*
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided
* that it is used in conjunction with NXP Semiconductors devices. This
* copyright, permission, and disclaimer notice must appear in all copies
* of this code.
********************************************************************************
#include "dram1.def";
* ### Channel 1 - uCore0 controls the injectors 1 and 2 ###
* ### Variables declaration ###
* Note: The data are stored into the dataRAM of the channel 1.
* Note: The Thold_tot variable defines the current profile time out.
* The active STARTx pin is expected to toggle in is low state before this time out.
* ### Initialization phase ###
init0: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ###
idle0: cwer CheckStart start row2; * Define entry table for high start pin
stoc on sssc; * Turn ON offset compensation
WaitLoop: wait row2; * uPC is stuck here for almost the whole idle time
CheckStart: joslr inj1_start start1; * Jump to inj1 if start 1 is high
joslr inj2_start start2; * Jump to inj2 if start 2 is high
jmpr WaitLoop;
* ### Shortcuts definition per the injector to be actuated ###
inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS
jmpr boost0; * Jump to launch phase
inj2_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT, VBOOST, LS
jmpr boost0; * Jump to launch phase
* ### Launch phase enable boost ###
boost0: stoc off sssc; * Turn OFF offset compensation
bias all on; * Enable all biasing structures, kept ON even during actuation
load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
cwer peak0 ocur row2; * Jump to peak phase when current is over threshold
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on
wait row12; * Wait for one of the previously defined conditions
* ### Peak phase continue on Vbat ###
peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count
cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold
stf high b0; * set flag0 high to release the DC-DC converter idle mode
peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
peak_off0: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
stos off off on; * Turn VBAT off, BOOST off, LS on
wait row123; * Wait for one of the previously defined conditions
* ### Bypass phase ###
bypass0: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
stos off off off; * Turn VBAT off, BOOST off, LS off
cwer hold0 tc3 row4; * Jump to hold when tc3 reaches end of count
wait row14; * Wait for one of the previously defined conditions
* ### Hold phase on Vbat ###
hold0: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
cwer eoinj0 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
cwer hold_on0 tc2 row3; * Jump to hold_on when tc2 reaches end of count
cwer hold_off0 ocur row4; * Jump to hold_off when current is over threshold
hold_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
stos off off on; * Turn VBAT off, BOOST off, LS on
wait row123; * Wait for one of the previously defined conditions
* ### End of injection phase ###
eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
jmpf jr2; * Jump back to idle phase
* ### End of Channel 1 - uCore0 code ###
*********************************************************************************
* ### Channel 1 - uCore1 controls the injectors 3 and 4 ###
* ### Variables declaration ###
* Note: The data that defines the profiles are shared between the two microcores.
* ### Initialization phase ###
init1: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ###
idle1: cwer CheckStart1 start row2; * Define entry table for high start pin
stoc on sssc; * Turn ON offset compensation
WaitLoop1: wait row2; * uPC is stuck here for almost the whole idle time
CheckStart1:joslr inj3_start start3; * Jump to inj1 if start 1 is high
joslr inj4_start start4; * Jump to inj2 if start 2 is high
jmpr WaitLoop1;
* ### Shortcuts definition per the injector to be actuated ###
inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS
jmpr boost1; * Jump to launch phase
inj4_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT, VBOOST, LS
jmpr boost1; * Jump to launch phase
* ### Launch phase enable boost ###
boost1: stoc off sssc; * Turn OFF offset compensation
load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
cwer peak1 ocur row2; * Jump to peak phase when current is over threshold
stf low b0; * set flag0 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on
wait row12; * Wait for one of the previously defined conditions
* ### Peak phase continue on Vbat ###
peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count
cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold
stf high b0; * set flag0 high to release the DC-DC converter idle mode
peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
peak_off1: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
stos off off on; * Turn VBAT off, BOOST off, LS on
wait row123; * Wait for one of the previously defined conditions
* ### Bypass phase ###
bypass1: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
stos off off off; * Turn VBAT off, BOOST off, LS off
cwer hold1 tc3 row4; * Jump to hold when tc3 reaches end of count
wait row14; * Wait for one of the previously defined conditions
* ### Hold phase on Vbat ###
hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
cwer eoinj1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
cwer hold_off1 ocur row4; * Jump to hold_off when current is over threshold
hold_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
wait row124; * Wait for one of the previously defined conditions
hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
stos off off on; * Turn VBAT off, BOOST off, LS on
wait row123; * Wait for one of the previously defined conditions
* ### End of injection phase ###
eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off
stf high b0; * set flag0 to high to release the DC-DC converter idle mode
jmpf jr2; * Jump back to idle phase
* ### End of Channel 1 - uCore1 code ###

8
firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def Normal file
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#define Iboost 0;
#define Ipeak 1;
#define Ihold 2;
#define Tpeak_off 3;
#define Tpeak_tot 4;
#define Tbypass 5;
#define Thold_off 6;
#define Thold_tot 7;

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firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc Normal file
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********************************************************************************
* Example Code
*
* Copyright(C) 2019 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* NXP products. This software is supplied "AS IS" without any warranties
* of any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights
* under any patent, copyright, mask work right, or any other intellectual
* property rights in or to any products. NXP Semiconductors reserves the
* right to make changes in the software without notification. NXP
* Semiconductors also makes no representation or warranty that such
* application will be suitable for the specified use without further testing
* or modification.
*
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided
* that it is used in conjunction with NXP Semiconductors devices. This
* copyright, permission, and disclaimer notice must appear in all copies
* of this code.
********************************************************************************
#include "dram2.def";
* ### Channel 2 - uCore0 controls dc-dc ###
* ### Initialization phase ###
init0: stgn gain5.8 ossc; * Set the gain of the opamp of the current measure block 4
load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L
load Isense4_high dac4h4n _ofs; * Load Isense4_high current threshold in DAC 4H
stdm null; * Set the boost voltage DAC access mode
cwer dcdc_idle _f0 row1; * Wait table entry for Vboost under Vboost_low threshold condition
cwer dcdc_on _vb row2; * Wait table entry for Vboost under Vboost_low threshold condition
cwer dcdc_off vb row3; * Wait table entry for Vboost over Vboost_high threshold condition
* ### Asynchronous phase ###
dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
stdcctl async; * Enable asynchronous mode
wait row13; * Wait for one of the previously defined conditions
* ### Synchronous phase ###
dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
stdcctl sync; * Enable synchronous mode
wait row12; * Wait for one of the previously defined conditions
* ### Idle phase ###
dcdc_idle: stdcctl sync; * Enable synchronous mode
jocr dcdc_idle _f0; * jump to previous line while flag 0 is low
jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high
* ### End of Channel 2 - uCore0 code ###
*********************************************************************************
* ### Channel 2 - uCore1 drives fuel pump ###
* ### Initialization phase ###
init1: stgn gain19.4 ossc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoact1; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ###
idle1: joslr act5_start start5; * Perform an actuation on act5 if start 5 (only) is active
joslr act6_start start6; * Perform an actuation on act6 if start 6 (only) is active
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
* ### Shortcuts definition per the injector to be actuated ###
act5_start: dfsct hs5 ls5 undef; * Set the 2 shortcuts: VBAT, LS
jmpr peak1; * Jump to launch phase
act6_start: dfsct hs5 ls6 undef; * Set the 2 shortcuts: VBAT, LS
jmpr peak1; * Jump to launch phase
* ### Launch peak phase on bat ###
peak1: load Ipeak dac_ossc _ofs; * Load the boost phase current threshold in the current DAC
cwer hold1 cur3 row2; * Jump to peak phase when current is over threshold
stos on on keep; * Turn VBAT off, BOOST on, LS on
wait row12; * Wait for one of the previously defined conditions
* ### Hold phase on Vbat ###
hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
load Ihold dac_ossc _ofs; * Load the hold current threshold in the DAC
cwer eoact1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
cwer hold_off1 cur3 row4; * Jump to hold_off when current is over threshold
hold_on1: stos on on keep; * Turn VBAT on, LS on
wait row124; * Wait for one of the previously defined conditions
hold_off1: ldcd rst _ofs off on Thold_off c2; * Load the length of the hold_off phase in counter 1 and turn VBAT off, LS on
wait row123; * Wait for one of the previously defined conditions
* ### End of injection phase ###
eoact1: stos off off keep; * Turn VBAT off, LS off
jmpf jr2; * Jump back to idle phase
* ### End of Channel 2 - uCore1 code ###

8
firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def Normal file
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#define Vboost_low 0;
#define Vboost_high 1;
#define Isense4_low 2;
#define Isense4_high 3;
#define Thold_off 4;
#define Thold_tot 5;
#define Ipeak 6;
#define Ihold 7;

19
firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin Normal file
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0000000000011000
0000000000000000
0000000000000000
0000000000000000
0000001100000011
0000000000000000
0000000000000000
0000000000011011
1100101000010010
0100101101001010
0000000000000000
0000000000110001
0000000000000000
0000000000000000
0000000000000000
0000001111111111
0000001111111111
0000000000000000
0000000000000000

19
firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin Normal file
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@ -0,0 +1,19 @@
0000000000011000
0000000000000000
0000000000000000
0000000000000000
0000110000000000
0000000000000000
0000000000000000
0000000000101010
0000110001111010
1110111001110001
0000000000000000
0000000000010000
0000000000000000
0000000000000000
0000000000000000
0000001111111111
0000001111111111
0000000000000000
0000000000000000

44
firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin Normal file
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@ -0,0 +1,44 @@
0001110111011010
0000000000001001
0000000000011110
0001110111011010
0000000000001001
0000000000011110
0000001010001110
0000000000001001
0000000000011110
0000001010001110
0000000000001001
0000000000011110
0000001010001110
0000000000001001
0000000000011110
0000001010001110
0000000000001001
0000000000011110
0000000000011110
0001110111011010
0000000001101001
0000000000011110
0001110111011010
0000000001101001
0000000000011110
0000001010001110
0000000001101001
0000000000011110
0000001010001110
0000000001101001
0000000000011110
0000000000000000
0000000000000000
0000000000011110
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000001

64
firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin Normal file
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@ -0,0 +1,64 @@
0000000011010100
0000000001101001
0000000001000001
0000000100001110
0000101110111000
0000000100001110
0000000100001110
1110101001100000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000

72
firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex Normal file
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@ -0,0 +1,72 @@
//
// Application:
// Asic ID: MC33816
// Version:
// DRAM
// Date: Thursday, December 26, 2019
// Author: Andrey
//
0x00D4,
0x0069,
0x0041,
0x010E,
0x0BB8,
0x010E,
0x010E,
0xEA60,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
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64
firmware/hw_layer/mc33816/rusefi/Registers/dram2.bin Normal file
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72
firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex Normal file
View File

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//
// Application:
// Asic ID: MC33816
// Version:
// DRAM
// Date: Thursday, December 26, 2019
// Author: Andrey
//
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44
firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin Normal file
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29
firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin Normal file
View File

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0000000000000011
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13
firmware/hw_layer/mc33816/rusefi/Simulator/AutoLoad.xml Normal file
View File

@ -0,0 +1,13 @@
<LoadDefault xmlns="http://tempuri.org/AutoLoad.xsd">
<MicroCodesReload ch1="True" ch2="True" ch3="True" />
<DPRamsReload ch1="True" ch2="True" ch3="True" />
<ChannelParametersReload ch1="True" ch2="True" ch3="True" />
<MainConfigurationReload reload="True" />
<DiagnosisConfigurationReload reload="True" />
<CrossbarConfigurationReload reload="True" />
<StimulusReload reload="True" />
<ActuatorReload reload="True" />
<FeedbackReload reload="True" />
<GraphicsReload reload="True" />
<ForceFlashEnable ch1="True" ch2="True" ch3="True" />
</LoadDefault>

16
firmware/hw_layer/mc33816/rusefi/Stimulus/stim.xml Normal file
View File

@ -0,0 +1,16 @@
<Stimuli>
<Stimulus target="Start1" time="1 ms" period="" value="high" />
<Stimulus target="Start1" time="3 ms" period="" value="low" />
<Stimulus target="Start3" time="1,100 us" period="" value="high" />
<Stimulus target="Start3" time="2,500 us" period="" value="low" />
<Stimulus target="Start5" time="1 ms" period="" value="high" />
<Stimulus target="Start5" time="2 ms" period="" value="low" />
<Stimulus target="Start7" time="1 ms" period="" value="high" />
<Stimulus target="Start7" time="3 ms" period="" value="low" />
<Stimulus target="Start4" time="2,600 us" period="" value="high" />
<Stimulus target="Start4" time="4 ms" period="" value="low" />
<Stimulus target="Start2" time="3,100 us" period="" value="high" />
<Stimulus target="Start2" time="3,900 us" period="" value="low" />
<Stimulus target="Start6" time="2,100 us" period="" value="high" />
<Stimulus target="Start6" time="3,900 us" period="" value="low" />
</Stimuli>

23
firmware/hw_layer/mc33816/rusefi/labels.xml Normal file
View File

@ -0,0 +1,23 @@
<?xml version="1.0" encoding="utf-8"?>
<AddressLabels>
<Channel1>
<uc0_Entrypoint>init0</uc0_Entrypoint>
<uc0_SwInterruptAddress>irq_sw</uc0_SwInterruptAddress>
<uc0_DriverDisabledAddress />
<uc0_DiagRoutineAddress>irq_auto</uc0_DiagRoutineAddress>
<uc1_Entrypoint>init1</uc1_Entrypoint>
<uc1_SwInterruptAddress />
<uc1_DriverDisabledAddress />
<uc1_DiagRoutineAddress />
</Channel1>
<Channel2>
<uc0_Entrypoint>init0</uc0_Entrypoint>
<uc0_SwInterruptAddress />
<uc0_DriverDisabledAddress />
<uc0_DiagRoutineAddress />
<uc1_Entrypoint>init1</uc1_Entrypoint>
<uc1_SwInterruptAddress />
<uc1_DriverDisabledAddress />
<uc1_DiagRoutineAddress />
</Channel2>
</AddressLabels>

473
firmware/hw_layer/mc33816/rusefi/project.xml Normal file
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@ -0,0 +1,473 @@
<Project xmlns="http://tempuri.org/project.xsd">
<Identifiers>
<Device>MC33816</Device>
<ECU>IDE Project</ECU>
<Application>%APPLICATION%</Application>
<DeviceName>%DEVICEID%</DeviceName>
<Version>rusefi</Version>
<Prefix>%PREFIX%</Prefix>
</Identifiers>
<Files>
<RegisterFile areaName="Main Configuration Registers (MCR)">Registers\main_config_reg.hex</RegisterFile>
<RegisterFile areaName="Channel 1 Configuration Registers (C1PR)">Registers\ch1_config_reg.hex</RegisterFile>
<RegisterFile areaName="Channel 2 Configuration Registers (C2PR)">Registers\ch2_config_reg.hex</RegisterFile>
<RegisterFile areaName="Channel 3 Configuration Registers (C3PR)">Registers\ch3_config_reg.hex</RegisterFile>
<RegisterFile areaName="Diagnosis Configuration Registers (DCR)">Registers\diag_config_reg.hex</RegisterFile>
<RegisterFile areaName="Crossbar Configuration Registers (XCR)">Registers\io_config_reg.hex</RegisterFile>
<MicroCodeFile channel="1" type="source" date="130995272773175445">MicrocodeCh1\ch1.psc</MicroCodeFile>
<MicroCodeFile channel="2" type="source" date="130995272773155443">MicrocodeCh2\ch2.psc</MicroCodeFile>
<MicroCodeFile channel="3" type="source" date="130995272773145442">MicrocodeCh3\ch3.psc</MicroCodeFile>
<DPramFile channel="1">Registers\dram1.hex</DPramFile>
<DPramFile channel="2">Registers\dram2.hex</DPramFile>
<DPramFile channel="3">Registers\dram3.hex</DPramFile>
<AutoLoadFile>Simulator\AutoLoad.xml</AutoLoadFile>
</Files>
<General>
<Clock>1 MHz</Clock>
</General>
<Windows>
<Structure x="0" y="0" xSize="280" ySize="240" state="Normal" visible="False" />
<Signals x="0" y="240" xSize="280" ySize="240" state="Normal" visible="False" />
<Micro x="0" y="0" xSize="574" ySize="692" state="Normal" visible="True">
<Hex8ForLine>True</Hex8ForLine>
<SeparateCompiledFolder>True</SeparateCompiledFolder>
<DPram channel="1" addressFormat="Hex">
<Entry address="0" format="Hex" unit="None" indexSelected="0" />
<Entry address="1" format="Hex" unit="None" indexSelected="0" />
<Entry address="2" format="Hex" unit="None" indexSelected="0" />
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</DPram>
<DPram channel="2" addressFormat="Hex">
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<Entry address="63" format="Hex" unit="None" indexSelected="0" />
</DPram>
<DPram channel="3" addressFormat="Hex">
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</DPram>
<RegisterArea name="Main Configuration Registers (MCR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
<RegisterArea name="Diagnosis Configuration Registers (DCR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
<RegisterArea name="Crossbar Configuration Registers (XCR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
<RegisterArea name="Channel 1 Configuration Registers (C1PR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
<RegisterArea name="Channel 2 Configuration Registers (C2PR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
<RegisterArea name="Channel 3 Configuration Registers (C3PR)">
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
<Reg>Hex</Reg>
</RegisterArea>
</Micro>
<Log x="22" y="22" xSize="836" ySize="307" state="Normal" visible="False" />
<Wave x="574" y="0" xSize="1342" ySize="692" state="Normal" visible="True" />
<Current x="574" y="692" xSize="1342" ySize="374" state="Normal" visible="True" />
<Stimulus x="0" y="0" xSize="504" ySize="368" state="Normal" visible="False" />
<Voltage x="0" y="0" xSize="580" ySize="357" state="Normal" visible="False" />
<Actuator x="0" y="692" xSize="574" ySize="374" state="Normal" visible="True" />
</Windows>
</Project>

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firmware/hw_layer/mc33816/rusefi/readme.md Normal file
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Completely default project as generated by MC33816 Dev Studio conveniently comes with default source code.