bump openocd fix #5223

misc/install/openocd/mem_helper.tcl

@@ -1,10 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Helper for common memory read/modify/write procedures
 
 # mrw: "memory read word", returns value of $reg
 proc mrw {reg} {
-	set value ""
+	return [read_memory $reg 32 1]
-	mem2array value 32 $reg 1
-	return $value(0)
 }
 
 add_usage_text mrw "address"
@@ -12,9 +12,7 @@ add_help_text mrw "Returns value of word in memory."
 
 # mrh: "memory read halfword", returns value of $reg
 proc mrh {reg} {
-	set value ""
+	return [read_memory $reg 16 1]
-	mem2array value 16 $reg 1
-	return $value(0)
 }
 
 add_usage_text mrh "address"
@@ -22,9 +20,7 @@ add_help_text mrh "Returns value of halfword in memory."
 
 # mrb: "memory read byte", returns value of $reg
 proc mrb {reg} {
-	set value ""
+	return [read_memory $reg 8 1]
-	mem2array value 8 $reg 1
-	return $value(0)
 }
 
 add_usage_text mrb "address"

misc/install/openocd/stm32f4discovery.cfg

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
 # http://www.st.com/internet/evalboard/product/252419.jsp
 

misc/install/openocd/stm32f4x.cfg

@@ -1,7 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f4x family
 
 #
-# stm32 devices support both JTAG and SWD transports.
+# stm32f4 devices support both JTAG and SWD transports.
 #
 source [find openocd/swj-dp.tcl]
 source [find openocd/mem_helper.tcl]
@@ -38,8 +40,6 @@ if { [info exists CPUTAPID] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
-tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
-
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
@@ -91,24 +91,30 @@ $_TARGETNAME configure -event examine-end {
 	mmw 0xE0042008 0x00001800 0
 }
 
-proc proc_post_enable {_chipname} {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
 	targets $_chipname.cpu
 
 	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
 		switch [$_chipname.tpiu cget -port-width] {
 			1 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
 				mmw 0xE0042004 0x00000060 0x000000c0
 				mmw 0x40021020 0x00000000 0x0000ff00
 				mmw 0x40021000 0x000000a0 0x000000f0
 				mmw 0x40021008 0x000000f0 0x00000000
 			  }
 			2 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
 				mmw 0xE0042004 0x000000a0 0x000000c0
 				mmw 0x40021020 0x00000000 0x000fff00
 				mmw 0x40021000 0x000002a0 0x000003f0
 				mmw 0x40021008 0x000003f0 0x00000000
 			  }
 			4 {
+				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
 				mmw 0xE0042004 0x000000e0 0x000000c0
 				mmw 0x40021020 0x00000000 0x0fffff00
 				mmw 0x40021000 0x00002aa0 0x00003ff0
@@ -116,11 +122,12 @@ proc proc_post_enable {_chipname} {
 			  }
 		}
 	} else {
+		# Set TRACE_IOEN; TRACE_MODE to async
 		mmw 0xE0042004 0x00000020 0x000000c0
 	}
 }
 
-$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
 
 $_TARGETNAME configure -event reset-init {
 	# Configure PLL to boost clock to HSI x 4 (64 MHz)

misc/install/openocd/stm32f7x.cfg

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f7x family
 
 #
@@ -107,13 +109,20 @@ $_TARGETNAME configure -event examine-end {
 	mmw 0xE0042008 0x00001800 0
 }
 
-$_TARGETNAME configure -event trace-config {
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+	targets $_targetname
+
 	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 	# change this value accordingly to configure trace pins
 	# assignment
 	mmw 0xE0042004 0x00000020 0
 }
 
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
+
 $_TARGETNAME configure -event reset-init {
 	# If the HSE was previously enabled and the external clock source
 	# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be

misc/install/openocd/stm32h7x.cfg

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32h7x family
 
 #
@@ -232,9 +234,7 @@ if {[set $_CHIPNAME.DUAL_CORE]} {
 
 # like mrw, but with target selection
 proc stm32h7x_mrw {used_target reg} {
-	set value ""
+	return [$used_target read_memory $reg 32 1]
-	$used_target mem2array value 32 $reg 1
-	return $value(0)
 }
 
 # like mmw, but with target selection

misc/install/openocd/stm32h7x_dual_bank.cfg

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32h7x family (dual flash bank)
 
 # STM32H7xxxI 2Mo have a dual bank flash.