F746
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rusefi
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c09ab97eda
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cd2043a9c9
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rem
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rem STM32F767 version of the firmware for Nucleo-F746ZG board
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rem
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cd ../../..
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set PROJECT_BOARD=NUCLEO_F746
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set PROJECT_CPU=ST_STM32F7
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set EXTRA_PARAMS=-DDUMMY -DSTM32F746xx ^
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-DEFI_INJECTOR_PIN3=GPIO_UNASSIGNED
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rem call compile_and_program.bat -r
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make -j1
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* ST32F746xG generic setup.
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*
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* RAM0 - Data, Heap.
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* RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
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*
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* Notes:
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* BSS is placed in DTCM RAM in order to simplify DMA buffers management.
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*/
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MEMORY
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{
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flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
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flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
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flash2 : org = 0x00000000, len = 0
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flash3 : org = 0x00000000, len = 0
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flash4 : org = 0x00000000, len = 0
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flash5 : org = 0x00000000, len = 0
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flash6 : org = 0x00000000, len = 0
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flash7 : org = 0x00000000, len = 0
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ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
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ram1 : org = 0x20010000, len = 240k /* SRAM1 */
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ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
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ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
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ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
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ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
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ram6 : org = 0x00000000, len = 0
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ram7 : org = 0x00000000, len = 0
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}
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/* For each data/text section two region are defined, a virtual region
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and a load region (_LMA suffix).*/
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/* Flash region to be used for exception vectors.*/
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REGION_ALIAS("VECTORS_FLASH", flash1);
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REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
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/* Flash region to be used for constructors and destructors.*/
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REGION_ALIAS("XTORS_FLASH", flash1);
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REGION_ALIAS("XTORS_FLASH_LMA", flash0);
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/* Flash region to be used for code text.*/
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REGION_ALIAS("TEXT_FLASH", flash1);
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REGION_ALIAS("TEXT_FLASH_LMA", flash0);
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/* Flash region to be used for read only data.*/
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REGION_ALIAS("RODATA_FLASH", flash0);
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REGION_ALIAS("RODATA_FLASH_LMA", flash0);
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/* Flash region to be used for various.*/
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REGION_ALIAS("VARIOUS_FLASH", flash1);
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REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
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/* Flash region to be used for RAM(n) initialization data.*/
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REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
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/* RAM region to be used for Main stack. This stack accommodates the processing
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of all exceptions and interrupts.*/
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REGION_ALIAS("MAIN_STACK_RAM", ram3);
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/* RAM region to be used for the process stack. This is the stack used by
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the main() function.*/
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REGION_ALIAS("PROCESS_STACK_RAM", ram3);
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/* RAM region to be used for data segment.*/
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REGION_ALIAS("DATA_RAM", ram0);
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REGION_ALIAS("DATA_RAM_LMA", flash0);
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/* RAM region to be used for BSS segment.*/
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REGION_ALIAS("BSS_RAM", ram3);
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/* RAM region to be used for the default heap.*/
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REGION_ALIAS("HEAP_RAM", ram0);
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/* Stack rules inclusion.*/
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INCLUDE ../NUCLEO_F767/rules_stacks.ld
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/*===========================================================================*/
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/* Custom sections for STM32F7xx. */
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/*===========================================================================*/
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/* RAM region to be used for nocache segment.*/
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REGION_ALIAS("NOCACHE_RAM", ram3);
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/* RAM region to be used for eth segment.*/
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REGION_ALIAS("ETH_RAM", ram3);
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SECTIONS
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{
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/* Special section for non cache-able areas.*/
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.nocache (NOLOAD) : ALIGN(4)
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{
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__nocache_base__ = .;
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*(.nocache)
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*(.nocache.*)
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*(.bss.__nocache_*)
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. = ALIGN(4);
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__nocache_end__ = .;
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} > NOCACHE_RAM
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/* Special section for Ethernet DMA non cache-able areas.*/
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.eth (NOLOAD) : ALIGN(4)
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{
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__eth_base__ = .;
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*(.eth)
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*(.eth.*)
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*(.bss.__eth_*)
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. = ALIGN(4);
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__eth_end__ = .;
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} > ETH_RAM
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}
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/* Code rules inclusion.*/
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INCLUDE ../NUCLEO_F767/rules_code.ld
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/* Data rules inclusion.*/
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INCLUDE ../NUCLEO_F767/rules_data.ld
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File diff suppressed because it is too large
Load Diff
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# List of all the board related files.
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BOARDSRC = $(PROJECT_DIR)/config/boards/NUCLEO_F767/board.c
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BOARDSRC_CPP = $(PROJECT_DIR)/config/boards/NUCLEO_F767/board_configuration.cpp
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# Required include directories
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BOARDINC = $(PROJECT_DIR)/config/boards/NUCLEO_F746 $(PROJECT_DIR)/config/stm32f7ems
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LDSCRIPT= $(PROJECT_DIR)/config/boards/NUCLEO_F746/STM32F746xG.ld
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# Override DEFAULT_ENGINE_TYPE
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DDEFS += -DDEFAULT_ENGINE_TYPE=CUSTOM_ENGINE -DSTM32F746xx
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