diff --git a/firmware/global.h b/firmware/global.h
index 1a9d54df2e..51a839b195 100644
--- a/firmware/global.h
+++ b/firmware/global.h
@@ -70,15 +70,20 @@ typedef unsigned int time_t;
 #if defined(STM32F4XX)
 // CCM memory is 64k
 #define CCM_OPTIONAL __attribute__((section(".ram4")))
+#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
 #define NO_CACHE	// F4 has no cache, do nothing
 #elif defined(STM32F7XX)
 // DTCM memory is 128k
 #define CCM_OPTIONAL __attribute__((section(".ram3")))
+//TODO: update LD file!
+#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
 // SRAM2 is 16k and set to disable dcache
 #define NO_CACHE __attribute__((section(".ram2")))
 #elif defined(STM32H7XX)
 // DTCM memory is 128k
 #define CCM_OPTIONAL __attribute__((section(".ram5")))
+//TODO: update LD file!
+#define SDRAM_OPTIONAL __attribute__((section(".ram8")))
 // SRAM3 is 32k and set to disable dcache
 #define NO_CACHE __attribute__((section(".ram3")))
 #else /* this MCU doesn't need these */
diff --git a/firmware/hw_layer/ports/stm32/stm32_common.mk b/firmware/hw_layer/ports/stm32/stm32_common.mk
index dcb836441c..a91a4a475c 100644
--- a/firmware/hw_layer/ports/stm32/stm32_common.mk
+++ b/firmware/hw_layer/ports/stm32/stm32_common.mk
@@ -14,3 +14,8 @@ RUSEFIASM = $(PROJECT_DIR)/hw_layer/ports/stm32/rusEfiStartup.S
 HW_INC += \
 	$(PROJECT_DIR)/hw_layer/ports/stm32 \
 	$(PROJECT_DIR)/hw_layer/ports/stm32/serial_over_usb
+
+ifeq ($(EFI_HAS_EXT_SDRAM), yes)
+	USE_OPT += -Wl,--defsym=STM32_HAS_SDRAM=1
+	DDEFS += -DEFI_HAS_EXT_SDRAM
+endif
diff --git a/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld b/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld
index 6ea690f3dc..32d9e26b79 100644
--- a/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld
+++ b/firmware/hw_layer/ports/stm32/stm32f4/STM32F4.ld
@@ -25,6 +25,10 @@
 /* STM32F42x and F46x have SRAM3 */
 RAM3_SIZE = DEFINED(STM32F4_HAS_SRAM3) ? 64k : 0;
 
+/* SDRAM */
+/* Only STM32F429I-Discovery has external SDRAM */
+SDRAM_SIZE = DEFINED(STM32_HAS_SDRAM) ? 8M : 0;
+
 MEMORY
 {
     bl      : org = 0x08000000, len = 16k     /* bootloader section */
@@ -43,7 +47,7 @@ MEMORY
     ram4    : org = 0x10000000, len = 64k       /* CCM SRAM */
     ram5    : org = 0x40024000, len = 4k        /* BCKP SRAM */
     ram6    : org = 0x00000000, len = 0
-    ram7    : org = 0x00000000, len = 0
+    ram7    : org = 0xD0000000, len = SDRAM_SIZE    /* SDRAM */
 }
 
 /* For each data/text section two region are defined, a virtual region
@@ -90,6 +94,9 @@ REGION_ALIAS("BSS_RAM", ram0);
 /* RAM region to be used for the default heap.*/
 REGION_ALIAS("HEAP_RAM", ram0);
 
+/* RAM region to be used for SDRAM segment.*/
+REGION_ALIAS("SDRAM_RAM", ram7);
+
 /* Bootloader section */
 SECTIONS
 {