manual sync

hardware/TLE8110ED_breakout_board/TLE8110ED.pro

@@ -1,32 +1,32 @@
-update=1/3/2019 3:43:39 PM
+update=1/8/2019 6:45:32 PM
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
 [cvpcb]
 version=1
 NetIExt=net
+[pcbnew]
+version=1
+PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
+LastNetListRead=
+PadDrill=0.6
+PadDrillOvalY=0.6
+PadSizeH=1.5
+PadSizeV=1.5
+PcbTextSizeV=1.5
+PcbTextSizeH=1.5
+PcbTextThickness=0.3
+ModuleTextSizeV=1
+ModuleTextSizeH=1
+ModuleTextSizeThickness=0.15
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+DrawSegmentWidth=0.2
+BoardOutlineThickness=0.09999999999999999
+ModuleOutlineThickness=0.15
 [eeschema]
 version=1
 LibDir=
@@ -34,3 +34,14 @@ LibDir=
 LibName1=TLE8110ED
 LibName2=conn
 LibName3=mechanical
+LibName4=power
+[schematic_editor]
+version=1
+PageLayoutDescrFile=../rusefi_lib/Border.kicad_wks
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60

hardware/TLE8110ED_breakout_board/TLE8110ED.sch

@@ -2,15 +2,16 @@ EESchema Schematic File Version 2
 LIBS:TLE8110ED
 LIBS:conn
 LIBS:mechanical
+LIBS:power
 LIBS:TLE8110ED-cache
 EELAYER 25 0
 EELAYER END
-$Descr USLetter 11000 8500
+$Descr A4 11693 8268
 encoding utf-8
 Sheet 1 1
-Title "TLE8110ED breakout board"
+Title "TLE8110ED low side driver chip"
-Date "2019-01-06"
+Date "2019-01-08"
-Rev "0.1"
+Rev "R0.1"
 Comp "rusEFI"
 Comment1 ""
 Comment2 ""
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 $EndSCHEMATC