diff --git a/firmware/CHANGELOG.md b/firmware/CHANGELOG.md index 02e89186ce..37ae8e38dc 100644 --- a/firmware/CHANGELOG.md +++ b/firmware/CHANGELOG.md @@ -53,6 +53,7 @@ Release template (copy/paste this for new release): - multi-line tooltips in TS #4927 - Negative temperature values for IAT Corr table #4941 - DC wastegate #4965 + - [LSE] RTC (SD log dates) #4556 ## December 2022 Release - "Day 289" diff --git a/firmware/ChibiOS b/firmware/ChibiOS index abd0e469c2..6b154adfaa 160000 --- a/firmware/ChibiOS +++ b/firmware/ChibiOS @@ -1 +1 @@ -Subproject commit abd0e469c2ee6c5b2b521c6a270e51b32454abad +Subproject commit 6b154adfaa56afe7570a19bbce552d2e7ea9b891 diff --git a/firmware/docs/rusEFI_custom_chibios.md b/firmware/docs/rusEFI_custom_chibios.md index 46e213052c..ba91498e17 100644 --- a/firmware/docs/rusEFI_custom_chibios.md +++ b/firmware/docs/rusEFI_custom_chibios.md @@ -1,10 +1,12 @@ rusEFI is trying to use latest stable ChibiOS with minimal changes -At the moment rusEFI uses https://github.com/rusefi/ChibiOS/tree/stable_18.2.rusefi +At the moment rusEFI uses https://github.com/rusefi/ChibiOS/tree/stable_20.3.x.rusefi rusEFI custom version of ChibiOS has the following changes: -# TODO this document has to be reviewed, seems to NOT be up to date with 18 patch +*) LSE auto-detection/fallback, RUSEFI_STM32_LSE_WAIT_MAX/RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL + +# TODO items below this line need to be reviewed, seems to NOT be up to date with 20.3 patch *) minor OS monitoring and maintainability fixes: chDbgStackOverflowPanic allows to know which thread has stack overflow @@ -12,8 +14,6 @@ rusEFI custom version of ChibiOS has the following changes: *) MMC timeout waitCounter -*) LSE auto-detection, see rusefi_lse_fix.h see LSE_TIMEOUT - *) Support for half/timeout-ISR for UART-DMA in /os/hal/include/uart.h and os/hal/ports/STM32/LLD/USARTv1/uart_lld.* by andreika Weird changes without an explanation: @@ -28,6 +28,5 @@ Weird changes without an explanation: New files: os/common/startup/SIMIA32/compilers/GCC/rules.mk - os/hal/ports/STM32/LLD/RTCv2/rusefi_lse_fix.h os/hal/ports/simulator/posix/* - \ No newline at end of file + diff --git a/firmware/hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h b/firmware/hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h index 11e71adc4c..ec4882b799 100644 --- a/firmware/hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h +++ b/firmware/hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h @@ -37,6 +37,10 @@ #define STM32F407_MCUCONF #define STM32F417_MCUCONF +// Allows LSE init to timeout and configure fallback RTC clock source in case +#define RUSEFI_STM32_LSE_WAIT_MAX 1000000 +#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSI + /* * HAL driver system settings. */ @@ -47,11 +51,8 @@ #ifndef STM32_HSE_ENABLED #define STM32_HSE_ENABLED TRUE #endif - -// rusEfi would automatically detect if we have 32768 quartz osc -// todo: apply LSE patch -#define STM32_LSE_ENABLED FALSE - +// see RUSEFI_STM32_LSE_WAIT_MAX +#define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI @@ -62,11 +63,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 -#if STM32_LSE_ENABLED - #define STM32_RTCSEL STM32_RTCSEL_LSE -#else - #define STM32_RTCSEL STM32_RTCSEL_LSI -#endif +// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL +#define STM32_RTCSEL STM32_RTCSEL_LSE #ifndef STM32_RTCPRE_VALUE #define STM32_RTCPRE_VALUE 8 #endif diff --git a/firmware/hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h b/firmware/hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h index 6a4b5c1b15..006e045344 100644 --- a/firmware/hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h +++ b/firmware/hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h @@ -59,6 +59,10 @@ #define STM32F7xx_MCUCONF +// Allows LSE init to timeout and configure fallback RTC clock source in case +#define RUSEFI_STM32_LSE_WAIT_MAX 1000000 +#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSI + /* * HAL driver system settings. */ @@ -69,7 +73,8 @@ #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE +// see RUSEFI_STM32_LSE_WAIT_MAX +#define STM32_LSE_ENABLED TRUE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSI @@ -80,11 +85,8 @@ #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 -#if STM32_LSE_ENABLED - #define STM32_RTCSEL STM32_RTCSEL_LSE -#else - #define STM32_RTCSEL STM32_RTCSEL_LSI -#endif +// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL +#define STM32_RTCSEL STM32_RTCSEL_LSE #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 diff --git a/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h b/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h index 988edf88d9..b81f5ac2dc 100644 --- a/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h +++ b/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h @@ -40,6 +40,10 @@ #define STM32H747_MCUCONF #define STM32H757_MCUCONF +// Allows LSE init to timeout and configure fallback RTC clock source in case +#define RUSEFI_STM32_LSE_WAIT_MAX 1000000 +#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL STM32_RTCSEL_LSI_CK + /* * General settings. */ @@ -74,7 +78,8 @@ #define STM32_CSI_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE #define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE +// see RUSEFI_STM32_LSE_WAIT_MAX +#define STM32_LSE_ENABLED TRUE #define STM32_HSIDIV STM32_HSIDIV_DIV1 /* @@ -123,7 +128,8 @@ * Reading STM32 Reference Manual is required. */ #define STM32_SW STM32_SW_PLL1_P_CK -#define STM32_RTCSEL STM32_RTCSEL_LSI_CK +// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL +#define STM32_RTCSEL STM32_RTCSEL_LSE_CK #define STM32_D1CPRE STM32_D1CPRE_DIV1 #define STM32_D1HPRE STM32_D1HPRE_DIV2 #define STM32_D1PPRE3 STM32_D1PPRE3_DIV2