diff --git a/board.mk b/board.mk
index f8b24c3..b152ed0 100644
--- a/board.mk
+++ b/board.mk
@@ -19,5 +19,7 @@ DDEFS += -DRAM_UNUSED_SIZE=100
 
 # USE_OPT += -Wl,--defsym=FLASH_SIZE=768k
 
-#Serial flash support
-#include $(PROJECT_DIR)/hw_layer/drivers/flash/sst26f_jedec.mk
+# This board uses ChibiOS MFS driver on external SPI flash
+include $(PROJECT_DIR)/hw_layer/ports/stm32/use_higher_level_flash_api.mk
+#Serial flash driver
+include $(PROJECT_DIR)/hw_layer/drivers/flash/sst26f_jedec.mk
diff --git a/board_storage.cpp b/board_storage.cpp
index e8418c0..067f848 100644
--- a/board_storage.cpp
+++ b/board_storage.cpp
@@ -1,5 +1,45 @@
 #include "pch.h"
 
-void boardInitMfs() {
+/* This board stores settings in external plain SPI flash */
+#if !defined(EFI_BOOTLOADER) && (EFI_STORAGE_MFS == TRUE)
 
-}
\ No newline at end of file
+#include "hal_serial_nor.h"
+#include "hal_mfs.h"
+
+/* Some fields in following struct are used for DMA transfers, so do not cache */
+NO_CACHE SNORDriver snor1;
+
+const SPIConfig SPIcfg1 = {
+	.end_cb			= NULL,
+	.error_cb		= NULL,
+	.dcr			= STM32_DCR_FSIZE(23U) |	/* 8MB device.          */
+					  STM32_DCR_CSHT(1U)		/* NCS 2 cycles delay.  */
+};
+
+const SNORConfig snorcfg1 = {
+	.busp			= &SPID1,
+	.buscfg			= &SPIcfg1
+};
+
+const MFSConfig mfsd_nor_config = {
+	.flashp			= (BaseFlash *)&snor1,
+	.erased			= 0xFFFFFFFFU,
+	.bank_size		= 64 * 1024U,
+	.bank0_start	= 0U,
+	.bank0_sectors	= 128U,	/* 128 * 4 K = 0.5 Mb */
+	.bank1_start	= 128U,
+	.bank1_sectors	= 128U
+};
+
+void boardInitMfs() {
+	/* Initializing and starting snor1 driver.*/
+	snorObjectInit(&snor1);
+	snorStart(&snor1, &snorcfg1);
+}
+
+const MFSConfig *boardGetMfsConfig()
+{
+	return &mfsd_nor_config;
+}
+
+#endif /* EFI_STORAGE_MFS == TRUE */
\ No newline at end of file